fifo – SyntaxBug

FPGA generates 3X3 image processing matrix through FIFO

In the previous series of articles on median filtering, I have written about the generation method of 3×3 matrix template: Median filter design based on FPGA—-(3) Matrix template generation module design_verilog image generation 3*3 matrix-CSDN blog Now it seems that this method is relatively crude and simple. The general processing method is to store an […]

Asynchronous FIFO design simulation based on Verilog HDL

1. What is asynchronous FIFO Asynchronous FIFO is one of the FIFO designs (First In First Out, data written first is read out first). Since read and write operations are independent, asynchronous FIFO is often used to transmit multi-bit data across clock domains. Asynchronous FIFO will be referred to as FIFO in the following. Under […]

C language to implement FIFO code

Recently, the author needed C language to implement a FIFO when working on a project, and started to refer to the following codes of these two masters. Great God One: C language to implement FIFO code_c language fifo-CSDN blog Great God Two: C language to implement FIFO code_c language fifo-CSDN blog Combining the advantages and […]

[[FIFO to BRAM IP interconnection, that is, AXIstream is transferred to the verilog code on BRAM]]

FIFO to BRAM IP interconnection, that is, AXIstream is transferred to the verilog code on BRAM control.v module control #( parameter TDATA_WIDTH = 32 , parameter BRAM_A_ADDR_WIDTH = 15 , parameter BRAM_din_WIDTH = 32 , parameter BRAM_B_ADDR_WIDTH = 15 )( input [TDATA_WIDTH – 1 : 0] tdata , input tvaild, input sys_clk, input sys_rst_n , […]

Verilog asynchronous FIFO implementation

module fifo_async#( parameter data_width = 32, parameter data_depth = 8, parameter addr_width = 4 ) ( input rst_n, input wr_clk, input wr_en, input [data_width-1:0] din, input rd_clk, input rd_en, output reg valid, output reg [data_width-1:0] dout, output empty, full output ); reg [addr_width:0] wr_addr_ptr;//Address pointer, one more bit than the address, MSB is used to […]

[[FIFO to multiplier to RAM verilog code and testbnench]]

Verilog code and testbnench for FIFO to multiplier to RAM Only the transmission of a single data is completed. Big data needs to be modified tb or basic connections. FIFO.v //synchronous fifo module FIFO_syn #( parameter WIDTH = 16, // the fifo wide parameter DEPTH = 1024, // depth parameter ADDR_WIDTH = clogb2(DEPTH) // bit […]

[[Verilog code asynchronous FIFO design explanation + source code + tb]]

Design of asynchronous FIFO Use Gray code to determine whether it is really full Used a very clever method Using gray code solves one problem, but it also brings another problem, that is, how to judge empty and full in the Gray code domain. The judgment of “empty” is still based on the fact that […]

Verilog function module – asynchronous FIFO with different read and write bit widths

Table of contents of FIFO series articles: Verilog function module – asynchronous FIFO-CSDN blog Verilog function module – synchronous FIFO-CSDN blog Verilog function module – asynchronous FIFO with different read and write bit widths-CSDN Blog Verilog function module – synchronous FIFO with different read and write bit widths-CSDN Blog Verilog function module – standard FIFO […]

Verilog function module – synchronous FIFO with different read and write bit widths

Linux inter-process communication IPC (pipe fifo mmap)

1. Introduction to inter-process communication: In the Linux environment, the address spaces of each process are independent of each other. Variables in any process are invisible in another process, so they cannot be accessed between processes. To exchange data, you must go through the kernel and open up a buffer in the kernel. Area, process […]