In the previous series of articles on median filtering, I have written about the generation method of 3×3 matrix template: Median filter design based on FPGA—-(3) Matrix template generation module design_verilog image generation 3*3 matrix-CSDN blog Now it seems that this method is relatively crude and simple. The general processing method is to store an […]
Tag: fpga
ZYNQ-FPGA-RTC (real-time display clock)
1. PCF8563 introduction The data generation of the real-time clock is completed through the PCF8563 module. PCF8563 has alarm function, timer function, time Clock output function and interrupt output function. Memory addresses 00H and 01H are used as control registers and status registers (CONTROL_STATUS); memory addresses 02H~08H are used as TIME timers (seconds~year timers); addresses […]
FPGA implements 3X3 convolution
Because the pixel data in FPGA are all pipeline inputs, they cannot be processed in parallel like CModel. Therefore, a 3*3 matrix acquisition module needs to be used to perform convolution operations with some operators. The specific implementation idea is to use two FIFOs to cache the data of the upper two rows respectively. When […]
FPGA module – serial port sending and receiving module
FPGA module – serial port module Send code receive code Pin constraints Send code 1. Use the sending module Using this module requires outputting a sending port output uart_txd, //UART send port /*————————————————-*/ wire uart_rx_done = 1’b1; //UART receives completion signal wire[7:0] rx_data; assign rx_data = 8’b11111111; //Data to be sent //parameter define parameter CLK_FREQ […]
FPGA—— Ultrasonic module based on ZYNQ ECO development board
Table of Contents Ultrasonic module led Ultrasonic ranging ultrasonic module `timescale 1ns / 1ps module SR_04( inputclk, input rst_n , input echo, //receiving end, determine the port return value output [15:0] dis , //final distance output trig //pulse is emitted ); parameter delay = (50*15) + (50*1000*100); //Period above 60ms parameter s1 = 0; //idle […]
FPGA—— based on ZYNQ ECO development board serial port
Table of Contents Serial port reception (RX) Serial port transmission (TX) Serial communication module Serial port reception (RX) `timescale 1ns / 1ps module UART_RX( inputclk, input rst_n, input rx, output rx_done , output [7:0] rx_data ); //parameter hz=50_00; //parameter bps = 96; parameter hz=50_000_000; parameter bps = 9600; parameter delay = hz/bps; wire rd_en; reg […]
FPGA-based pipeline divider
Directory Preface 1. Basic principles of divider 2. Pipeline divider programming 3. Simulation verification Summarize Foreword Hello, everyone! This is Xiao Rui. In this article, we will introduce the design of pipeline divider in FPGA. 1. Basic principles of divider Dividers are more complex than multipliers, and there are many implementation algorithms, such as restoring […]
FPGA—— based on ZYNQ ECO development board marquee
Table of Contents always statement Assignment statements (blocking assignment statements and non-blocking assignment statements) bit concatenation operator marquee always statement In Verilog, the always statement is an important statement used to describe combinational logic or sequential logic. Its declaration format is as follows: always @() can contain various signals, such as input ports, registers or […]
FPGA finds the maximum value and the second maximum value
Click the blue words to follow us Follow and star the public account, and exciting content will be delivered every day Source: Internet material Implement a module on FPGA to find the maximum value and second maximum value among 32 inputs. 32 inputs are given by one clock cycle. (The questions are from forums and […]
[FPGA Development] About how to use FPGA to configure AD9528
In this work, I came into contact with the AD9528, a clock generation chip from Arnold & Son, which can generate multiple synchronous clocks. This clock uses the spi interface to configure accordingly. Later, I will record how I wrote the corresponding FPGA code for this process. AD9528 basic introduction: Specific configuration parameters and methods: […]