Article directory
- Introduction to WDG
- iWDG
- IWDG timeout calculation
- WWDG
- WWDG timeout and window value settings
- Independent watchdog project
- WWDG project
Introduction to WDG
WDG watchdog (Watchdog Timer) is a common hardware device. In the STM32F10 series, there are two kinds of watchdogs, namely independent watchdog and window watchdog, which can be used to monitor the operation of the system. status, and take corresponding measures when the system fails or stops running to ensure the stability and reliability of the system.
WDG watchdog generally uses a timer and a dog feeding mechanism. The counter will count periodically. When the number of times counted by the counter reaches the threshold, an interrupt or system reset will be generated. The dog feeding mechanism is to regularly feed the watchdog to the watchdog when the system is running normally, that is, to reset the counter count. value to prevent the timer from reaching the threshold and causing a system reset.
The IWDG independent watchdog generates the clock frequency from the built-in low-speed clock (LSI), which is effective even if the main clock fails;
Applicable scenarios: It can work independently outside the main program and requires low clock accuracy.
The WWDG window watchdog is driven by the APB1 clock divided by
Applicable scenarios: In situations where accuracy requirements are relatively high, it is often used to monitor irreversible errors or stuck software faults in programming programs.
IWDG
The clock frequency generated by the independent watchdog is generally considered to be 40kHz (LSI clock frequency is set at 30kHz to 60kHz). The timer can be reset through an 8-bit prescaler to a 12-bit down counter;
12-bit down counter, which means it can count up to 4095 numbers, decreases from large to small, and generates a reset when it reaches the threshold;
Prescaler register:
7 frequency division coefficients can be adjusted
Status register:
They are to perform status detection on the update of the reload value and the update of the prescaler value respectively; For multiple reload values and prescaler values, the RVU and PVU must be cleared before the values can be changed again.
Reload registers:
Reloading the register is also called feeding the dog. It needs to be controlled through the key register to load the reload value into the counter.
Key register (emphasis):
For the independent watchdog, it needs to be enabled through the key register. Enter a specific value 0xCCCC to turn it on; when it starts for the first time, it starts counting down from 0xFFF and generates a reset when it reaches 0; then it is loaded to the specified value by reloading the value;
Both the prescaler register and the reload value register are protected by the watchdog. To use the watchdog, you must unprotect them before they can be used. Enter 0x5555 to unprotect them;
The reloading value needs to be executed by the 0xAAAA command.
| Write the value of the key register | Execute |
|---|---|
| 0xAAAA | The value in IWDG_RLR is reloaded into the counter (feeding the dog) |
| 0xCCCC | Enable watchdog |
| 0x5555 | Unprotect the IWDG_PR and IWDG_RLR registers |
IWDG timeout calculation
40kHz is 0.025ms when inverted; the count value range is limited to between 4096 and 0; since calculation starts from 0, the count value needs to be increased by 1;
WWDG
The clock frequency is generated by PCLK1 and passed to the 6-bit down counter through the prescaler; when the watchdog is started, the WDGA (activation bit) will be set to ‘1’, T6:0 is compared with W6:0, only T6 :0 is greater than W6:0 to generate ‘1’; in this way, the result and CR activation bit ‘1’ generates ‘1’ through the AND gate to reach the OR gate; the lower line of the OR gate is when the watchdog is allowed to generate an interrupt, decrement When the counter reaches 0x40, an early wake-up interrupt (EWI) will be generated, which can also cause WWDG to generate a reset; finally reaching the AND gate, the ‘1’ generated by the OR gate and the activation bit ‘1’ can generate a reset.
The down counter here only has 6 bits, but reaches 7 bits in the CR register, so stipulates that when the down counter is less than 0x40, that is, when the T6 bit changes from 1 to 0, a reset will occur;
So the value in the CR register must be between 0xFF and 0xC0;
From the block diagram, we can know that the count value must be greater than the window value. If the count value is less than the window value, that is, if the dog is fed too quickly, a reset will also occur;
Notice:
WWDG timeout and window value settings
WDGTB is the time base, and the time base raised to the power of 2 is the prescaler value, which will produce divisions of 1, 2, 4, and 8; 4096 is the CK clock frequency generated by dividing PCLK1 by 4096;
Window value:
Independent watchdog project
wiring:
Use the screen to observe whether it is the effect of watchdog reset;
int main()
{<!-- -->
OLED_Init();
Key_Init();
OLED_ShowString(1,1,"WatchDog:");
if(RCC_GetFlagStatus(RCC_FLAG_IWDGRST)==SET)
{<!-- -->
OLED_ShowString(2,1,"IWDG RST");
Delay_ms(500);
OLED_ShowString(2,1," ");
Delay_ms(100);
//Clear flag bit
RCC_ClearFlag();
}
else
{<!-- -->
OLED_ShowString(3,1,"RST");
Delay_ms(500);
OLED_ShowString(3,1," ");
Delay_ms(100);
}
//Initialize watchdog, LSI clock has been turned on
IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);//Unprotect PR RLR
IWDG_SetPrescaler(IWDG_Prescaler_16);//Set the frequency division value
IWDG_SetReload(2499);//Set the loading value
IWDG_Enable();//Start independent watchdog
//Loop to feed the dog
while(1)
{<!-- -->
uint8_t num=Key_GetNum(); // Keep pressing the key to indicate a crash
IWDG_ReloadCounter();//Feed the dog
OLED_ShowString(4,1,"Feeding");
Delay_ms(800);
OLED_ShowString(4,1," ");
Delay_ms(180);
}
}
When the watchdog reset occurs, a reset flag will be generated. Use this feature to check whether a watchdog reset occurs. If so, “IWDG RST” will flash on the screen. Otherwise, “RST” will flash to indicate a system reset;
For initializing the watchdog we perform operations according to the block diagram;
There is a provision here that LSI will be forced to open, so don’t worry about it;
Next is to remove the protection:
The timeout value here is set to 1000ms. According to the figure above, the frequency division is at least 16;
Calculation shows that the counter value is 2500; (It can also be other frequency divisions. My test results are similar, close to 980ms, and a reset will occur when it exceeds 980ms);
Finally start the watchdog:
After that, the dog is continuously fed in the loop. After testing, the dog feeding time is at least 980ms under 16 frequency division, which is still relatively large compared to the actual 1000ms;
We can also press and hold the button. Since we use the loop method, if we keep pressing and holding the button, the program will get stuck. Therefore, if we cannot feed the dog in time, a watchdog reset will occur;
WWDG Project
The wiring diagram is consistent with the above; the thinking method is also consistent with the above;
#include "stm32f10x.h" // Device header
#include "Delay.h"
#include "OLED.h"
#include "Key.h"
int main()
{<!-- -->
OLED_Init();
Key_Init();
OLED_ShowString(1,1,"WatchDog:");
if(RCC_GetFlagStatus(RCC_FLAG_WWDGRST)==SET)
{<!-- -->
OLED_ShowString(2,1,"WWDG RST");
Delay_ms(500);
OLED_ShowString(2,1," ");
Delay_ms(100);
//Clear flag bit
RCC_ClearFlag();
}
else
{<!-- -->
OLED_ShowString(3,1,"RST");
Delay_ms(500);
OLED_ShowString(3,1," ");
Delay_ms(100);
}
//Initialize watchdog
RCC_APB1PeriphClockCmd(RCC_APB1ENR_WWDGEN,ENABLE);//Turn on the clock
WWDG_SetPrescaler(WWDG_Prescaler_8);//Set the prescaler value
WWDG_SetWindowValue(21|0x40);//Set window value 30ms
WWDG_Enable(54|0x40);//Start and set the count value 50ms
//Loop to feed the dog
while(1)
{<!-- -->
Key_GetNum(); // Keep pressing the key to indicate a crash
OLED_ShowString(4,1,"Feeding");
Delay_ms(20);
OLED_ShowString(4,1," ");
Delay_ms(19);
WWDG_SetCounter(54|0x40);
}
}
During the initialization process, the PCLK1 clock of APB1 needs to be turned on;
We need to set a window value of 30ms and a timeout value of 50ms;
From the above figure, we can see that our prescaler value is at least 8, and then the counter value is about 55.
The same goes for setting the window value:
After calculation, the corresponding value T5:0-W5:0=33, W5:0 is 21;
Things to note here:
You cannot put the reprint value in the front position,
The reason is that the time for feeding the dog is too short and has not yet reached the window value; the solution is to put it after the delay, or you can judge whether it is the first time to feed the dog, and skip it if it is the first time; to solve the problem.
After final testing, the dog feeding interval is between 31ms and 50ms (including 31 and 50), which is relatively accurate (relatively independent watchdog). If it is represented by the flashing ‘Feeding’ used above, then the interval is [31 -49], because there is a delay in executing the statement.