Article directory
-
- What is VIO
- ip configuration
- fword and top-level modules
- debug
- matlab verification
The goal of experiment 1 is to change the frequency of the sine wave generated by dds through vio, test it through ila, and also check whether the waveform file is correct in matlab
Regarding dds and ila, I have discussed it in detail in my previous blog. Here I introduce vio ip
What is VIO
The VIO (Virtual Input/Output) IP core in Vivado is an IP core used for debugging and testing FPGA designs. It allows designers to check the running status of the design and modify its behavior by reading and writing registers inside the FPGA using the JTAG interface. The VIO IP core provides a simple and easy-to-use interface that allows users to easily interact with FPGA internal registers.
?By using the VIO IP core, users can monitor and modify signals in the design in real time for debugging and verification. In addition, VIO IP cores can be used with other IP cores and design components to help designers better understand and debug the entire system.
? Mainly used for virtual IO; the output of VIO can control the input of the module, and the input of VIO can display the output value of the module.
ip configuration
Or configure dds ip first:
?
?
?Set the number of bits to 2 to control four frequency control words and obtain four sine waves with different frequencies.
?Add ila
?
?
fword and top-level modules
fword_set has simulated key switching frequency
`timescale 1ns / 1ps
//simulated key part
module Fword_set(
inputclk,
input rst_n ,
input [1:0] key_PINC ,
output reg [23:0] Fword
);
always@(*)
begin
case(key_PINC)
0: Fword <= 'h51eb; //1Mhz 20971.52 rounded to 20971
1: Fword <= 'ha3d7; //2Mhz 41943.04 rounded to 41943
2: Fword <= 'hf5c2; //3Mhz 62914.56 rounded to 62914
3: Fword <= 'h33333; //10Mhz 209715.2 rounded to 209715
endcase
end
endmodule
module vio_top(input clk,input rstn); wire [1:0] key_PINC; wire s_axis_config_tvalid,m_axis_data_tvalid,m_axis_phase_tvalid; wire [23:0] m_axis_phase_tdata,Fword; wire [7:0]m_axis_data_tdata; assign s_axis_config_tvalid=1'b1; dds_compiler_0 dds_compiler_u ( .aclk(clk), // input wire aclk .s_axis_config_tvalid(s_axis_config_tvalid), // input wire s_axis_config_tvalid .s_axis_config_tdata(Fword), // input wire [23 : 0] s_axis_config_tdata .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid .m_axis_data_tdata(m_axis_data_tdata), // output wire [7 : 0] m_axis_data_tdata .m_axis_phase_tvalid(m_axis_phase_tvalid), // output wire m_axis_phase_tvalid .m_axis_phase_tdata(m_axis_phase_tdata) // output wire [23 : 0] m_axis_phase_tdata ); vio_0 vio_u ( .clk(clk), // input wire clk .probe_out0(key_PINC) // output wire [1 : 0] probe_out0 ); ila_0 ila_u ( .clk(clk), // input wire clk .probe0(key_PINC), // input wire [1:0] probe0 .probe1(Fword), // input wire [23:0] probe1 .probe2(m_axis_data_tdata) // input wire [7:0] probe2 ); Fword_set Fword_u( .clk (clk), .rst_n (rstn ), .key_PINC (key_PINC ), //output .Fword (Fword) ); endmodule
Debugging
During debugging, we can continuously modify the value of vio to observe different simulation results.
?key_PINC[1]=0, key_PINC[0]=0 waveform, at this time one cycle is about 25 steps
?
The waveform of key_PINC[1]=1, key_PINC[0]=0, at this time, one cycle is about 13 steps long
?
The waveform of key_PINC[1]=1, key_PINC[0]=0, at this time, one cycle is about 7 steps.
?
?In the above hardware test, a sine wave with an output frequency of 1MHz has a cycle length of approximately 25 units; a sine wave with an output frequency of 2MHz has a cycle length of approximately 13 units; and a sine wave with an output frequency of 3MHz has a cycle length of approximately 13 units. It’s about 7 units long. According to the multiple relationship between the output frequencies, it can be judged that the corresponding relationship between the periods is correct.
matlab verification
Export the simulation results of the three situations as csv files to matlab for analysis
?
matlab code
csv1_row6 = ila0{<!-- -->:,7}; The sixth column of data in %iladata_1MHz.csv file
csv2_row6 = ila1{<!-- -->:,7}; The sixth column of data in %iladata_2MHz.csv file
csv3_row6 = ila2{<!-- -->:,7}; The sixth column of data in %iladata_3MHz.csv file
fs=50000000; %Set the sampling frequency to 50MHz
N=2048; % sampling points
n=0:N-1;
t=n/fs;
f=n*fs/N; %frequency sequence
figure;
subplot(2,1,1);plot(t,csv1_row6);grid on;title('Sine wave corresponding to 1MHz output frequency');
y1=abs(fft(csv1_row6,N));
subplot(2,1,2);plot(f,y1,'r');grid on;title('Spectrum corresponding to 1MHz output frequency');
figure;
subplot(2,1,1);plot(t,csv2_row6);grid on;title('Sine wave corresponding to 2MHz output frequency');
y2=abs(fft(double(csv2_row6),N));
subplot(2,1,2);plot(f,y2,'r');grid on;title('Spectrum corresponding to 2MHz output frequency');
figure;
subplot(2,1,1);plot(t,csv3_row6);grid on;title('Sine wave corresponding to 3MHz output frequency');
y3=abs(fft(double(csv3_row6),N));
subplot(2,1,2);plot(f,y3,'r');grid on;title('Spectrum corresponding to 3MHz output frequency');
The first peak is at 2Mhz and the second peak is at 48Mhz (conjugate symmetry feature)
The first peak is at 4Mhz and the second peak is at 46Mhz (conjugate symmetry feature)
The first peak is at 6Mhz and the second peak is at 44Mhz (conjugate symmetry feature)
