EDA experiment—–Design of four-bit multiplier (QuartusII)

Table of Contents

1. Experimental purpose

2. Experimental equipment

3. Experimental principles

4. Experimental content

5. Experimental steps

6. Experimental results

7. Experimental process

1. Multiplier principle

2. Programming ideas and programming implementation

3. Simulation test

4.Circuit connection

5. File burning

1. Experimental purpose

  1. Understand the principles of four-bit parallel multipliers.
  2. Understand the design ideas of four-bit parallel multipliers.
  3. Master the method of using Verilog language to implement basic binary operations.
  4. Master the basic syntax of Verilog language.

2. Experimental equipment

  1. One PC;
  2. An FPGA experiment box.

3. Experimental Principle

There are many ways to implement parallel multipliers, but they can be basically divided into two categories. One is implemented by combinational logic circuits, and the other is implemented by pipelines. The biggest advantage of parallel multipliers with a pipeline structure is that they are fast. Especially in multipliers with continuous input, they can achieve almost a single-cycle operation speed, but the implementation is slightly more complicated than a combinational logic circuit. The following is a detailed introduction to the method of implementing unsigned number multiplication in combinational logic circuits. If there is a multiplicand A and a multiplier B, first multiply the lowest bits of A and B to get S1, then shift A to the left by 1 bit and multiply with the second bit of B to get S2, and then shift A to the left by 3 bits. Multiply with the third digit of B to get S3, and so on until all the digits of B are multiplied, and then add the multiplied results S1, S2, S3… to get the multiplication result. It should be noted that the specific implementation of the multiplier is not a real multiplication, but a simple judgment. Let’s take a simple example. If A is shifted to the left by n bits and then multiplied by the nth bit of B, if the bit of B is ‘1’, then the intermediate result of the multiplication is the result of A being shifted to the left by n bits. Otherwise, if the bit of B is ‘1’ 0′, then just let the intermediate result of the multiplication be 0. After the multiplication of all bits of B is completed, add all the intermediate results to obtain the result of the multiplication of A and B.

Basic grammar knowledge you need to master in this experiment:

1. Use of parameter definition keyword parameter;

2. Usage of for statement;

3. Shift operators and their usage.

(Reference: Verilog HDL Language Basics-CSDN Blog)

4. Experimental content

The task of this experiment is to implement a simple four-bit parallel multiplier. The multiplicand A is represented by SW1~SW4 of the dip switch module, the multiplier B is represented by four independent buttons, and the multiplication result is represented by D1 of the LED module. ~D8 to represent, LED light means the corresponding bit is ‘1’. The toggle switch inputs a four-digit multiplicand and a four-digit multiplier, and the data obtained after multiplication by the designed circuit is displayed on the LED light.

5. Experimental steps

A

212,213,34,35

B

153,95 ,154,31

LED[7:0],LED_CS

167,165,166,162,164,159,161,156,174
  1. Open the QUARTUSII software and create a new project.
  2. After completing the project, create a new Verilog File and open the Verilog editor dialog box.
  3. Write Verilog programs in the Verilog editing window according to the experimental principles and your own ideas.
  4. After writing the Verilog program, save it. Compile and simulate the Verilog program written, and correct errors in the program.
  5. After the compilation and simulation are correct, assign the pins according to the table below. After the allocation is completed, perform full compilation again to make the pin allocation effective. (The pin interface is shown in the table below)
  6. Use the download cable to load the corresponding sof file into the FPGA through the JTAG port.
  7. Select the clock of digital signal source module F to 1kHz, flip the corresponding toggle switch, and enter a four-digit multiplier (SW5-SW8) and Multiplicand (key1-key4), observe the result displayed on the luminous tubes D1-D8 (the light is on indicating that the corresponding bit is 1) and record it. Observe whether the experimental results are consistent with your own programming ideas.
  8. After the experiment is completed, turn off the power and organize the experimental equipment.

6. Experimental results

After the design file is loaded into the target device, flip the corresponding DIP switch and enter a four-digit multiplier and multiplicand, and the binary number of the result of multiplying these two values will be displayed on the LED light.

Seven. Experimental Process

1. Multiplier principle

The multiplier is an arithmetic component that is often faced in the processor design process. Under normal circumstances, multiplication can be directly processed by comprehensive tools or by calling the ready-made IP of EDA manufacturers. The advantage of this method is that it is fast and reliable, but it also has its shortcomings, such as affecting the reproducibility of the same design between different tool platforms. Portability, timing area optimization methods are limited, and personalized design requirements cannot be met. Therefore, it is still necessary to be familiar with and master the underlying implementation principles of multipliers. Having many skills will always come in handy, and it is also a reflection of the solid basic skills of an IC design engineer.

The multiplication process without using any optimization algorithm can be illustrated by the column-vertical multiplication we learned in elementary school. Starting from the low digit of the multiplier, one digit is taken each time and multiplied by the multiplicand, and the product is temporarily stored as a partial product. After all significant digits of the multiplier are multiplied, all partial products are calculated according to the weights of the corresponding multiplier digits. The values are shifted and accumulated to obtain the final product. As shown in the figure below, the left side shows the decimal multiplication process with the base 10, and the right side shows the binary multiplication process with the base 2. PP0~PP3 respectively represent the partial products after each multiplication. It can be seen that there is essentially no difference between binary multiplication and decimal multiplication.

2. Programming ideas and programming implementation

According to the principle of the multiplier, if the number of digits of the multiplier and multiplicand is m and n respectively, then the number of digits of the multiplied result is m + n-1 digits.

Here we will get two input data, which are the multiplier and the multiplicand. We can traverse each digit of the multiplier. If the number of digits currently traversed by the multiplier is 1, then the result number is added The upper multiplicand is shifted one bit to the left; if the traversal reaches 0, no operation is performed and the next loop traversal is performed directly.

Create Verilog file

Then proceed to programming, the code is as follows:

module test_04(
A,B,R
);
input [3:0] A,B;
parameter s=4;
output [7:0] R;
integer i;
reg [7:0] R;
always@(A or B)
begin
R=0;
for(i=0;i<s;i=i + 1)
begin
if(B[i]==1)//If the current bit of the multiplier is 1, perform an addition and left shift operation on the result
R=R + (A<<i);
end
end
endmodule

Then set it as the top-level file to compile and run. If the results are correct, we can conduct simulation experiments.

3. Simulation test

Create a simulation file, as shown in the figure:

Then double-click the blank area here (left mouse button)

Then click here to set the parameters

Then, first click List to list the parameter variables, then click where the arrow below points, move these parameters right to the current waveform simulation file, and finally click OK.

Then go to the parameter settings, click on the position pointed by the upper arrow, and set the automatic increasing parameters. The lower arrow points to the period, which can be customized.

Finally, compile and run to generate the simulation waveform. The result is as follows:

After the simulation test is correct, we can connect the circuit.

4.Circuit connection

Right-click the Verilog file and click Generate submodule file.

After there are no problems, create the block file, as shown in the picture:

Open the component and click on the project file, we can see the component written in our Verilog language, and then just take it out and use it.

The last step is to connect the circuit diagram. When connecting the circuit diagram, because the input and output have multiple widths, you need to use a bus to connect. After that, you need to modify the input and output names, and then add the width of the variable! ! !

Then bind the pins, and the result is as follows:

Finally, the whole thing is compiled and run. After there are no errors, we can proceed with the burning operation.

5. File burning

click here.

Here we can see that there is a chip, That is the sof file we generated. You only need to burn this file to your development board. (Note: If No Hardware is displayed above, click on the interface settings next to it and set it to the USB interface. It will be automatically displayed when the development board is connected).

That’s all for this issue, see you next time!

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