, glitch-free clock switching circuit, also called Glitch free circuit, clock seamless switching circuit, I have encountered it in the written test. If you have not been exposed to it, you may not know how to start.
As more and more multi-clocks are used in today’s chips (especially in the communications field), it is often necessary to switch clock sources while the chip is running. The usual implementation is tomultiplex two clock sources of different frequencies in hardware and control the multiplexer MUX through internal logic.
The two clocks may be completely unrelated in frequency, or they may be exponentially related. No matter what the situation is, glitches may occur when opening and closing the gate. A glitch on the clock line is dangerous to the entire system because it may edge-trigger some registers while leaving others untouched.
In this article, two different ways are used to avoid glitches on the output clock. The first method is suitable for two clocks whose frequencies are multiples, and the second method is suitable for two unrelated clocks.
1. The problem of real-time clock switching
The problem with on-the-fly clock switching
Figure 1 shows a simple implementation of clock switching using AND-OR gates to form a multiplexer MUX.
Pure combinational logic clock switching, because it is level triggered, will inevitably produce glitches;
This clock switching multiplexer has 1 control signal SELECT, when SELECT = 0 it outputs CLK0, when SELECT = 1 it outputs CLK1.
When the value of SELECT changes, the output clock switches from the current clock source to the next clock source, and glitches may occur at this time.
As shown in the timing diagram in Figure 1-1, when the SELECT control signal changes, a glitch is generated on the output OUT CLOCK. The problem with this type of gated switch is that theSELECT switch control signal can change at any level of the clock source, causing the output clock to be truncated or glitched.
TheSELECT control signal is likely to be generated by one of the two input clock sources to drive the flip-flop. This means that if the frequencies of the two clock sources are multiples, then there is a known relationship between SELECT and the two clock sources. timing relationship, otherwise SELECT may be asynchronous to at least one clock source.
Regardless of whether the frequency or phase relationship between multiple input clock sources is known or not, switching cannot be performed in the high-level state of these clock sources (any high level is not possible, that is, for Figure 1, it must be in Switch when both input clock sources are low). If the two clock sources have a fixed relationship, a fixed delay can be used to reduce the difference between the start and end times of the two clock sources. Fixed delays cannot be used if the input frequency is unknown or the clocks are irrelevant.
2. Seamless switching of related clocks
Glitch protection for related clock sources
Figure 2-1 shows the glitch-free switching solution for the relevant clock sources. Insert a falling-edge active D flip-flop in the selection path of each clock source.
(Why is the falling edge here? Reference: Gating clock and control signal level, AND gate gating, OR gate gating, rising edge gating, falling edge gating)
The selection control signal SELECT is registered at each falling edge of the clock, and a new clock selection is enabled only after the selection of other clocks is released (invalidated), which effectively solves the output glitch problem.
Registering the selection control signal at the falling edge of the clock ensures that the control signal will not transition at the high level of the two clock sources, thus preventing the output clock from being truncated (truncation causes glitches).
The selection of one clock is fed back to another clock (two QN, i.e. ~Q). This feedback mechanism makes the gate switch must cancel the output selection of the current clock before selecting to output the next clock, thus avoiding Any glitches that may appear.
Assume that SELECT transitions at a moderate high level at this time. Due to the action of the AND gate, it is necessary to wait for the register output QN triggered by another clock to also change to 1 before the result of the AND gate SELECT-1 will change, and The change of QN needs to wait until the falling edge of the clock before changing, so the transition of the processed SELECT-1 signal only occurs at the low level of the clock.
The timing diagram in Figure 2-2 shows how the waveform of the output OUT CLOCK is affected when the SELECT signal changes from 0 to 1. First stop the output of CLK0 on OUT CLOCK on the falling edge of CLK0, and then start outputting CLK1 on the following falling edge of CLK1.
module glitch_2 (
input clk0,
input clk1,
input select,
input rst_n,
outputclkout
);
reg out1;
reg out0;
always @(negedge clk1 or negedge rst_n)begin
if(rst_n == 1'b0)begin
out1 <= 0;
end
else begin
out1 <= ~out0 & amp; select;
end
end
always @(negedge clk0 or negedge rst_n)begin
if(rst_n == 1'b0)begin
out0 <= 0;
end
else begin
out0 <= ~select & amp; ~out1;
end
end
assign clkout = (out1 & amp; clk1) | (out0 & amp; clk0);
endmodule
Analysis:
1. When select=0, the output of F1 is always 0, so the output is affected by F0 and clk0, and the input of F0 is always 1, so the output is only affected by clk0 and is in phase;
2. When select=1, the output is affected by F1. However, since F0 has been 1 for a period of time before, input 0 will only be read at the falling edge of clk0. At this time, the output maintains the previous state. When the falling edge of clk1 comes, it starts In phase with clk1; then who determines the output after the falling edge of clk0 and before the falling edge of clk1?
3. After the falling edge of the stop position of clk0 comes, the lower input of the OR gate is 0, and the output of clk1 at the previous moment has always been 0, so the output is still 0; when the falling edge of the clk1 clock comes, it is known that seelct becomes 1 , the output will change according to clk1 in the future.
There are 3 timing paths in this circuit that require special consideration:
(1) SELECT control signal to any flip-flop that is valid on the falling edge;
(2) The output of DFF0 is connected to the input of DFF1;
(3) The output of DFF1 goes to the input of DFF0.
If the signal on any of these three paths changes during the capture edge of the destination register clock, there is a certain chance that the output of the register will enter a meta-stable state, which means it will enter an ideal 0 A state between and 1. (In this example, the capture edges are both falling edges).
The metastable state will randomly stabilize to 0 or 1 after a period of time, which causes the two registers to collect different values (one is considered to be 0, and the other is considered to be 1). Therefore, this requires that the two register capture edges and the initiation edge of the SELECT signal be separated to avoid any possible asynchronous interface. Since the timing relationship between the two clock sources is known, the above can be achieved by using appropriate multi-cylce hold or minimum delay constraints.
When the chip is started, both the DFF0 and DFF1 registers should be reset to the “0” state, so that at the beginning, neither clock is selected for output. The clock switch has built-in fault tolerance by starting both flip-flops in the “0” state.
Suppose there is a bug at startup that causes one of the clocks to not toggle. If the initial state of the flip-flop using this wrong clock is the “1” state, and this flip-flop is not triggered by the flip edge of the clock, the output state of the register remains unchanged, which prevents the triggering of another clock. choose. By starting both registers with a “0” state, even if one clock is not working properly, the other clock can be gated out.
3. Seamless switching of irrelevant clocks
Glitch protection for unrelated clock sources
In the former gating selection method to avoid output glitches, the frequencies of the two input clock sources are required to be multiples, so that the user can (by using appropriate timing constraints) avoid signals being asynchronous to either clock domain. This implementation has no mechanism for handling asynchronous signals.
In this way,a second implementation is proposed, using synchronous circuits to avoid potential metastability risks brought by asynchronous signals. When the two clock sources are completely uncorrelated, asynchronous behavior may come from SELECT, or it may come from an asynchronous feedback signal from another clock domain.
As shown in Figure 3-1, for each clock source path, add a flip-flop driven by the rising edge of this clock source to avoid metastability . The addition of rising-edge active flip-flops on the clock source path, together with the existing falling-edge active flip-flops, is used to reduce the probability of potential metastability caused by SELECT or asynchronous feedback signals.
A synchronizer built using a simple two-level register. The first-level register stabilizes the data by latching the data, and then transmits the stabilized data to the second-level flip-flop, which is interpreted by other parts of the circuit. .
Circuit function: Two asynchronous clock source switching circuits;
The role of DFF1 and DFF3 (each path is the first two flip-flops): Insert a rising edge flip-flop in the selected path to cache data and pass the data to the next level; if removed, it will The circuit generates metastable states caused by asynchronous signals;
The reason why DFF2 and DFF4 use negative edges (the last two flip-flops on each path): SELECT is ANDed with the feedback output, and the falling edge sampling feedback can ensure thatafter a clock is completely deselected , the output will output another clock to avoid glitches.
module glitch_DFF (
input clk0,
input clk1,
input select,
input rst_n,
outputclkout
);
wire B;
reg DFF3Q, DFF4Q, DFF4_Q; //DFF4Q=Q, DFF4_Q=~Q
wire A;
reg DFF1Q, DFF2Q, DFF2_Q; //DFF2Q=Q, DFF2_Q=~Q
assign A = select & DFF4_Q;
assign B = ~select & DFF2_Q;
//The first level flip-flop uses rising edge sampling, and the AND operation of the selection signal and the feedback signal
always@(posedge clk1 or negedge rst_n) begin
if(~rst_n)
DFF1Q <= 0;
else
DFF1Q <= A;
end
//The second level flip-flop uses falling edge sampling
always@(negedge clk1 or negedge rst_n) begin
if(~rst_n) begin
DFF2Q <= 0;
DFF2_Q <= 1;
end
else begin
DFF2Q <= DFF1Q;
DFF2_Q <= ~DFF1Q;
end
end
//================================================ ====================
//The first level flip-flop uses rising edge sampling, and the AND operation of the selection signal and the feedback signal
always@(posedge clk0 or negedge rst_n) begin
if(~rst_n)
DFF3Q <= 0;
else
DFF3Q <= B;
end
//The second level flip-flop uses falling edge sampling
always@(negedge clk0 or negedge rst_n) begin
if(~rst_n) begin
DFF4Q <= 0;
DFF4_Q <= 1;
end
else begin
DFF4Q <= DFF3Q;
DFF4_Q <= ~DFF3Q;
end
end
wire E, F;
assign E = clk1 & DFF2Q;
assign F = clk0 & DFF4Q;
assign clkout = E | F;
endmodule
4. Conclusion
Conclusion
Through the technology introduced in this article, glitches generated during clock switching can be avoided with little overhead. These technologies are completely scalable and can be used for switching multiple clocks. For multiple clock sources, the selected signal source for each clock is fed back to all other clock sources.