code
diff --git a/pmon/arch/mips/ls7a/ht.h b/pmon/arch/mips/ls7a/ht.h
index 7bddf501..099d630a 100644
--- a/pmon/arch/mips/ls7a/ht.h
+ + + b/pmon/arch/mips/ls7a/ht.h
@@ -64,6 + 64,8 @@
#define LS3A_HT_RX_UNCACHE_WIN0_OFFSET 0xF0
#define LS3A_HT_RX_UNCACHE_WIN1_OFFSET 0xF8
#define LS3A_HT_RX_UNCACHE_WIN2_OFFSET 0x168
+ #define LS3A_HT_TX_POST_WIN0_OFFSET 0x170
+ #define LS3A_HT_TX_POST_WIN1_OFFSET 0x178
#define LS7A_HT_RX_WIN0_OFFSET 0x140
#define LS7A_HT_RX_WIN1_OFFSET 0x148
diff --git a/pmon/arch/mips/ls7a/ls3a7a_ht_init.S b/pmon/arch/mips/ls7a/ls3a7a_ht_init.S
index a24ac816..a0dfb31f 100644
--- a/pmon/arch/mips/ls7a/ls3a7a_ht_init.S
+ + + b/pmon/arch/mips/ls7a/ls3a7a_ht_init.S
@@ -142,6 + 142,12 @@ ls3a7a_ht_init:
and a0, a0,a1
sw a0, 0x50(t0)
+ li a0, 0x0040fffc
+ sw a0, (LS3A_HT_TX_POST_WIN0_OFFSET + 4)(t0)
+ li a0, 0x80000000
+ sw a0, (LS3A_HT_TX_POST_WIN0_OFFSET)(t0)
+
+
//2. 7A side HT configure begin
//!!!note: use t1 store 7A side HT controller address as global variable
//open RX space
@@ -158,13 + 164,25 @@ ls3a7a_ht_init:
li a1, 0x80000000
sw a1, (LS7A_HT_RX_WIN1_OFFSET + 0)(t1)
-#if 0 //enable DMA post write
+ #if 1 //enable DMA post write
TTYDBG("Enable 7A HT Post space.\r\\
")
//window0 00_0000_0000-7f_ffff_ffff
li a1, 0x00008000
sw a1, (LS7A_HT_TX_POST_WIN0_OFFSET + 4)(t1)
li a1, 0x80000000
sw a1, (LS7A_HT_TX_POST_WIN0_OFFSET + 0)(t1)
+ li a1, 0x80008000
+ sw a1, (LS7A_HT_TX_POST_WIN1_OFFSET + 4)(t1)
+ li a1, 0x80000000
+ sw a1, (LS7A_HT_TX_POST_WIN1_OFFSET + 0)(t1)
+ lw a0, 0x1c4(t1)
+ li a1, (0x1 << 11)
+ not a1, a1
+ and a0, a0,a1
+ sw a0, 0x1c4(t1)
+
+ li a1, 0x40
+ sb a1, 0x1c7(t1)
#endif
//set csr_dw_write to 1'b0 to transfer write mask information when write data less than 32Byte
diff --git a/pmon/arch/mips/ls7a/ls7a_config.S b/pmon/arch/mips/ls7a/ls7a_config.S
index 81de307c..9468f06a 100644
--- a/pmon/arch/mips/ls7a/ls7a_config.S
+ + + b/pmon/arch/mips/ls7a/ls7a_config.S
@@ -231,3 + 231,15 @@ pd_145:
jrra
nop
.end ls7a_get_pcie_dll_score
+
+ .global ls7a_version
+ .ent ls7a_version
+ .set noreorder
+ .set mips3
+ ls7a_version:
+ dli v1, 0x90000efdfe000100
+lb v0, 0x8(v1)
+ jr ra
+ nop
+ .end ls7a_version
+
diff --git a/pmon/arch/mips/ls7a/ls7a_init.S b/pmon/arch/mips/ls7a/ls7a_init.S
index c4b93653..a41e9e6c 100644
--- a/pmon/arch/mips/ls7a/ls7a_init.S
+ + + b/pmon/arch/mips/ls7a/ls7a_init.S
@@ -1095,6 + 1095,19 @@ cal_one_pcie_x8:
and a0, a0, t3
sw a0, 0x58(t1)
+ li a0, 0
+ sw a0, 0x24(t1)
+bal ls7a_version
+ nop
+ beqz v0,1f
+ nop
+ lw a0, 0x24(t1)
+ or a0, 4
+ sw a0, 0x24(t1)
+ lw a0, 0x28(t1)
+ or a0, 1
+ sw a0, 0x28(t1)
+ 1:
dli t1, 0x90000e0060000000
li a0, 0xff204c
@@ -1157,6 + 1170,21 @@ cal_one_pcie_x8:
and a0, a0, t3
sw a0, 0x58(t1)
+ li a0, 0
+ sw a0, 0x24(t1)
+
+bal ls7a_version
+ nop
+ beqz v0,1f
+ nop
+ lw a0, 0x24(t1)
+ or a0, 4
+ sw a0, 0x24(t1)
+ lw a0, 0x28(t1)
+ or a0, 1
+ sw a0, 0x28(t1)
+ 1:
+
dli t1, 0x90000e0060100000
li a0, 0xff204c
sw a0, 0x0(t1)
@@ -1205,6 + 1233,20 @@ cal_one_pcie_x8:
lw a0, 0x58(t1)
and a0, a0, t3
sw a0, 0x58(t1)
+
+ li a0, 0
+ sw a0, 0x24(t1)
+bal ls7a_version
+ nop
+ beqz v0,1f
+ nop
+ lw a0, 0x24(t1)
+ or a0, 4
+ sw a0, 0x24(t1)
+ lw a0, 0x28(t1)
+ or a0, 1
+ sw a0, 0x28(t1)
+ 1:
dli t1, 0x90000e0060200000
li a0, 0xff204c
@@ -1254,6 + 1296,20 @@ cal_one_pcie_x8:
lw a0, 0x58(t1)
and a0, a0, t3
sw a0, 0x58(t1)
+
+ li a0, 0
+ sw a0, 0x24(t1)
+bal ls7a_version
+ nop
+ beqz v0,1f
+ nop
+ lw a0, 0x24(t1)
+ or a0, 4
+ sw a0, 0x24(t1)
+ lw a0, 0x28(t1)
+ or a0, 1
+ sw a0, 0x28(t1)
+ 1:
dli t1, 0x90000e0060300000
li a0, 0xff204c
@@ -1359,6 + 1415,21 @@ cal_one_pcie_x8:
and a0, a0, t3
sw a0, 0x58(t1)
+ li a0, 0
+ sw a0, 0x24(t1)
+
+bal ls7a_version
+ nop
+ beqz v0,1f
+ nop
+ lw a0, 0x24(t1)
+ or a0, 4
+ sw a0, 0x24(t1)
+ lw a0, 0x28(t1)
+ or a0, 1
+ sw a0, 0x28(t1)
+ 1:
+
dli t1, 0x90000e0060000000
li a0, 0xff204c
sw a0, 0x0(t1)
@@ -1419,6 + 1490,20 @@ cal_one_pcie_x8:
lw a0, 0x58(t1)
and a0, a0, t3
sw a0, 0x58(t1)
+
+ li a0, 0
+ sw a0, 0x24(t1)
+bal ls7a_version
+ nop
+ beqz v0,1f
+ nop
+ lw a0, 0x24(t1)
+ or a0, 4
+ sw a0, 0x24(t1)
+ lw a0, 0x28(t1)
+ or a0, 1
+ sw a0, 0x28(t1)
+ 1:
dli t1, 0x90000e0060100000
li a0, 0xff204c
@@ -1538,7 + 1623,21 @@ cal_one_pcie_x8:
lw a0, 0x58(t1)
and a0, a0, t3
sw a0, 0x58(t1)
+
+ li a0, 0
+ sw a0, 0x24(t1)
+bal ls7a_version
+ nop
+ beqz v0,1f
+ nop
+ lw a0, 0x24(t1)
+ or a0, 4
+ sw a0, 0x24(t1)
+ lw a0, 0x28(t1)
+ or a0, 1
+ sw a0, 0x28(t1)
+ 1:
dli t1, 0x90000e0060000000
li a0, 0xff204c
sw a0, 0x0(t1)
@@ -1600,6 + 1699,20 @@ cal_one_pcie_x8:
and a0, a0, t3
sw a0, 0x58(t1)
+ li a0, 0
+ sw a0, 0x24(t1)
+
+bal ls7a_version
+ nop
+ beqz v0,1f
+ nop
+ lw a0, 0x24(t1)
+ or a0, 4
+ sw a0, 0x24(t1)
+ lw a0, 0x28(t1)
+ or a0, 1
+ sw a0, 0x28(t1)
+ 1:
dli t1, 0x90000e0060100000
li a0, 0xff204c
sw a0, 0x0(t1)
@@ -1719,6 + 1832,20 @@ cal_one_pcie_x8:
and a0, a0, t3
sw a0, 0x58(t1)
+ li a0, 0
+ sw a0, 0x24(t1)
+
+bal ls7a_version
+ nop
+ beqz v0,1f
+ nop
+ lw a0, 0x24(t1)
+ or a0, 4
+ sw a0, 0x24(t1)
+ lw a0, 0x28(t1)
+ or a0, 1
+ sw a0, 0x28(t1)
+ 1:
dli t1, 0x90000e0060000000
li a0, 0xff204c
@@ -1780,7 + 1907,21 @@ cal_one_pcie_x8:
lw a0, 0x58(t1)
and a0, a0, t3
sw a0, 0x58(t1)
+
+ li a0, 0
+ sw a0, 0x24(t1)
+bal ls7a_version
+ nop
+ beqz v0,1f
+ nop
+ lw a0, 0x24(t1)
+ or a0, 4
+ sw a0, 0x24(t1)
+ lw a0, 0x28(t1)
+ or a0, 1
+ sw a0, 0x28(t1)
+ 1:
dli t1, 0x90000e0060100000
li a0, 0xff204c
sw a0, 0x0(t1)
@@ -1899,7 + 2040,21 @@ cal_one_pcie_x8:
lw a0, 0x58(t1)
and a0, a0, t3
sw a0, 0x58(t1)
+
+ li a0, 0
+ sw a0, 0x24(t1)
+bal ls7a_version
+ nop
+ beqz v0,1f
+ nop
+ lw a0, 0x24(t1)
+ or a0, 4
+ sw a0, 0x24(t1)
+ lw a0, 0x28(t1)
+ or a0, 1
+ sw a0, 0x28(t1)
+ 1:
dli t1, 0x90000e0060000000
li a0, 0xff204c
sw a0, 0x0(t1)
@@ -1960,7 + 2115,22 @@ cal_one_pcie_x8:
lw a0, 0x58(t1)
and a0, a0, t3
sw a0, 0x58(t1)
+
+ li a0, 0
+ sw a0, 0x24(t1)
+bal ls7a_version
+ nop
+ beqz v0,1f
+ nop
+ lw a0, 0x24(t1)
+ or a0, 4
+ sw a0, 0x24(t1)
+ lw a0, 0x28(t1)
+ or a0, 1
+ sw a0, 0x28(t1)
+ 1:
+
dli t1, 0x90000e0060100000
li a0, 0xff204c
sw a0, 0x0(t1)