Preface
Today is October 5, 2023. I have just completed my vacation back to Hunan. In this fiercely competitive Shenzhen, I hope that everyone can maintain a strong learning spirit like me every day. My mind is very open, as long as it is not a company Confidential, I think the things you learn can be made available for free. Charging is not called learning, it is called buying key technical points (in fact, many times you can’t use them well after buying them, so it’s better to learn step by step by yourself). I also hope that everyone will support Unisoc’s FPGA and SOCP series product lines. Today I will talk about instantiation. The instantiation TOP is difficult for many beginners to master. In addition to my article, you can read more about this general knowledge point written by others. I hope that domestic chip design will get better and better, and foreign chips can also maintain their own characteristics and develop together.
Create a project
This time, we take ZYNQ MPSOC ZU2CG development board as an example:
Add the main chip and so on to generate a block design of design_1.
Add an AXI GPIO IP.
Automatically generated code
Doesn’t this code look very complicated, and does it change every time it is revised?
why? Because your initialization top-level is this, it’s time to design a top-level yourself and instantiate this module.
Design the TOP top-level architecture yourself
Create a new top.v
And a lot of modifications to the code are as follows:
`timescale 1ns / 1ps
//
//Company:
// Engineer:
//
// Create Date: 2023/10/04 12:19:24
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
//Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 – File Created
// Additional Comments:
//
//
module top(
LED1_tri_o,//These must be defined in TOP
sys_clk_p, //The clock is defined
sys_clk_n,
sys_rst_n,
led//Test LED is well defined
);
output [0:0]LED1_tri_o;
wire [0:0]axi_gpio_0_GPIO_TRI_O;
wire [39:0]ps8_0_axi_periph_M00_AXI_ARADDR;
wire ps8_0_axi_periph_M00_AXI_ARREADY;
wire ps8_0_axi_periph_M00_AXI_ARVALID;
wire [39:0]ps8_0_axi_periph_M00_AXI_AWADDR;
wire ps8_0_axi_periph_M00_AXI_AWREADY;
wire ps8_0_axi_periph_M00_AXI_AWVALID;
wire ps8_0_axi_periph_M00_AXI_BREADY;
wire [1:0]ps8_0_axi_periph_M00_AXI_BRESP;
wire ps8_0_axi_periph_M00_AXI_BVALID;
wire [31:0]ps8_0_axi_periph_M00_AXI_RDATA;
wire ps8_0_axi_periph_M00_AXI_RREADY;
wire [1:0]ps8_0_axi_periph_M00_AXI_RRESP;
wire ps8_0_axi_periph_M00_AXI_RVALID;
wire [31:0]ps8_0_axi_periph_M00_AXI_WDATA;
wire ps8_0_axi_periph_M00_AXI_WREADY;
wire [3:0]ps8_0_axi_periph_M00_AXI_WSTRB;
wire ps8_0_axi_periph_M00_AXI_WVALID;
wire [0:0]rst_ps8_0_96M_peripheral_aresetn;
wire [39:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_ARADDR;
wire [1:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_ARBURST;
wire [3:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_ARCACHE;
wire [15:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_ARID;
wire [7:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_ARLEN;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_ARLOCK;
wire [2:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_ARPROT;
wire [3:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_ARQOS;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_ARREADY;
wire [2:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_ARSIZE;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_ARVALID;
wire [39:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_AWADDR;
wire [1:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_AWBURST;
wire [3:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_AWCACHE;
wire [15:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_AWID;
wire [7:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_AWLEN;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_AWLOCK;
wire [2:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_AWPROT;
wire [3:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_AWQOS;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_AWREADY;
wire [2:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_AWSIZE;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_AWVALID;
wire [15:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_BID;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_BREADY;
wire [1:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_BRESP;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_BVALID;
wire [31:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_RDATA;
wire [15:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_RID;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_RLAST;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_RREADY;
wire [1:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_RRESP;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_RVALID;
wire [31:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_WDATA;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_WLAST;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_WREADY;
wire [3:0]zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_WSTRB;
wire zynq_ultra_ps_e_0_M_AXI_HPM0_LPD_WVALID;
wire zynq_ultra_ps_e_0_pl_clk0;
wire zynq_ultra_ps_e_0_pl_resetn0;
assign LED1_tri_o[0] = axi_gpio_0_GPIO_TRI_O;
input sys_clk_p;
input sys_clk_n;
input sys_rst_n;
output [1:0]led;
design_1 design_1_wrapper**//Instantiate the block that has been changing just now**
(
.LED1_tri_o(LED1_tri_o)
);
led_twinkle led_twinkle_wrapper**//Instantiate IP for LED flashing**
(
.sys_clk_p(sys_clk_p),
.sys_clk_n(sys_clk_n),
.sys_rst_n(sys_rst_n),
.led(led)
);
endmodule
Design constraints
#IO pin constraints
#Clock cycle constraints
create_clock -name sys_clk_p -period 10 [get_ports sys_clk_p]
#clock pin
set_property IOSTANDARD DIFF_HSTL_I_12 [get_ports sys_clk_p]
set_property IOSTANDARD DIFF_HSTL_I_12 [get_ports sys_clk_n]
set_property PACKAGE_PIN AE5 [get_ports sys_clk_p]
set_property PACKAGE_PIN AF5 [get_ports sys_clk_n]
#reset pin
set_property -dict {PACKAGE_PIN AH11 IOSTANDARD LVCMOS33} [get_ports sys_rst_n]
#LEDLight
set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS33} [get_ports {led[0]}]
set_property -dict {PACKAGE_PIN AF10 IOSTANDARD LVCMOS33} [get_ports {led[1]}]
set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33} [get_ports {LED1_tri_o[0]}]
The LED flashing program led_twinkle.v in the code-this is the test routine of punctual atoms.
`timescale 1ns / 1ps
// Copyright ?************************************/ /
//Yuanzige online teaching platform: www.yuanzige.com
//Technical support: www.openedv.com
//Taobao store: http://openedv.taobao.com
//Follow the WeChat public platform WeChat account: “Zhengdian Atom” to obtain ZYNQ & FPGA & STM32 & LINUX information for free.
//Copyright, piracy will be investigated.
//Copyright? Punctual Atom 2018-2028
//All rights reserved
//———————————————— —————————————-
// File name: led_twinkle
// Last modified Date: 2021/10/13 10:55:56
// Last Version: V1.0
// Descriptions: LED light flashes
//———————————————— —————————————-
// Created by: punctual atom
// Created date: 2021/10/13 10:55:56
// Version: V1.0
// Descriptions: The original version
//
//———————————————— —————————————-
// ****************** ******************************//
module led_twinkle(
input sys_clk_p , //system differential input clock
input sys_clk_n , //system differential input clock
input sys_rst_n, //system reset, active low level
output [1:0] led //LED light
);
//reg define
reg [26:0] cnt;
//************************************************ *****
//** main code
//************************************************ *****
//Judge the value of the counter to output the status of the LED
assign led = (cnt < 27’d5000_0000) ? 2’b01 : 2’b10 ;
//assign led = (cnt < 27’d5) ? 2’b01 : 2’b10 ; //only for simulation
//Convert differential signal
IBUFDS diff_clock
(
.I (sys_clk_p), //system differential input clock
.IB(sys_clk_n), //System differential input clock
.O (sys_clk) //Output system clock
);
//The counter counts between 0~10000_0000
always @ (posedge sys_clk or negedge sys_rst_n) begin
if(!sys_rst_n)
cnt <= 27’d0;
else if(cnt < 27’d10000_0000)
//else if(cnt < 27’d10) //only for simulation
cnt <= cnt + 1’b1;
else
cnt <= 27’d0;
end
endmodule
Take a look at the effect. Flash by flash, if you add more IP, it will change to TOP. come on.