OSERDESE2 primitive-parallel-to-serial conversion

1. Data parallel-serial conversion

– an OSERDESE
The data in the 2-module parallel-to-serial converter receives 2~8 bits from
FPGA
Parallel data within logical structures (if using OSERDESE2
width extension, then 14 bits), serialize the data, and pass
OQ output passes it to IO B
. Parallel data is serialized in order from lowest to highest data input pin, i.e.
D
The data on the 1 input pin is the first bit sent to the OQ
on the pin. Data Parallel – The serial converter has two modes, Single Data Rate
,
SDR
) and double data rate
(Double Data Rate
,
DDR
).

OSERDESE
2 Use the clock
CLK
and
CLKDIV
Perform data rate conversion.
CLK
is a high-speed serial clock,

C L K D IV
is the divided parallel clock.
CLK
and
CLKLDIV
Must be phase aligned. Before using this module, OSERDESE must be
2 Apply reset. O
SERDESE
2 Contains an internal counter to control data flow.

2. Three-state parallel-to-serial converter

In addition to parallel-to-serial conversion of data, OSERDESE
2 The module also contains a parallel-to-serial converter for tri-state control of the IOB. Unlike data conversion, tri-state converters can only serialize up to 4-bit parallel tri-state signals. Tri-state converters cannot be cascaded.

3. Pin contact analysis

1. Schematic diagram

2.Basic circuit diagram

3. Pin analysis

(1) O
Q
: The output width is 1), the data path is only output to
IOB
.

(2)
OFB
: output (width 1), datapath output fed back to
ISERDESE
2 or connect to
ODELAYE
2 .

(3)
TQ
: Output (width is 1), to
IO B
Three-state control output.

(4)
TFB
: Output, to
F P G A
Three-state control output within the internal logic structure.

(5)
SHIFT
0
U T
1: Output (width is 1), carry data output for width expansion. Connect to main

O
SERDESE
2 of
SHIFTIN
1 0
SERDESE
2 .

(6)
SHIFT
0
UT
2: Output (width is 1), carry data output is used for width expansion. Connect to main
OSERDESE
2

of
SHIFTIN
2O
SERDESE
2 .

(7)
C L
: Input (width is 1), high-speed clock input.

(8)
C LK D IV
: Input (width is 1), divided clock input. clock delay elements, deserialized data, and
CE unit.

(9)
D
1?
D
8: Input (each width is 1), parallel data input.

(10)
TCE
: Input (width 1), tri-state clock enabled.

(11)
OCE
: Input (width is 1), output data clock enabled.

(12)
TB Y TEIN
: Input (width is 1), byte group three-state input.

(13)
TBYTEO U T
: Output (width is 1), byte group tri-state output.

(14)
RST
: Input (width is 1), active high reset.

(15)
SHIFTIN
1: The input width is 1), and the carry data width is extended by the input. connect to from
OSERDESE
2 SHIFTOUT
1.

(16)
SHIFTIN
2: Input (width is 1), carry data width expansion input. Connect to from
OSERDESE
2

of
SH
1
FTOUT
2 .

(17)
T
1?
T
4: Input (each width is 1), parallel three-state input.

Properties of the OSERDESE2 primitive

Attributes	Description	Value	Default value
D A T A _ R A T E _ O Q	Is it defined on every clock edge or only on The rising edge of the clock changes data ( O Q )	String: S D R or D D R	D D R
D A T A _ R A T E _ T Q	Is it defined on every clock edge or only on The rising edge of the clock changes the three states ( T Q ) , or Set to buffer E Configuration	String: B U F/SD R /D D R	D D R
D A T A _ W ID T H	Define the width of the parallel-to-serial data converter Spend . This value depends on D A T A _ R A T E _ O Q value	Integer: 2 , 3 , 4 , 5 , 6 , 7 , 8, 10 or 1 4 . exist S D R mode, 2 , 3 , 4 , 5, 6, 7 ,and 8 It is effective . exist D D R mode, 2 , 4 , 6 , 8 , 1 0 and 1 4 It is effective	4
S E R D E S one M O D E	When using width extension, define O S E R D E S E 2 Is it the master or the slave?	String: M A S T E R /S L A V E	M A S T E R
T R IS T A T E one W ID TH	Define parallel – serial 3 Width of state converter	Integer: 1 or 4	4
T B Y T E _ C T L	Only for passing MIG tools	F A L S E /T R U E	F A L S E
T B Y T E one S R C	Only for passing M 丨 G tool	F A L S E /T R U E	F A L S E

4. Master-slave connection diagram

4. Application method

I believe you don’t want to read the nonsense above, so let’s show you something practical and useful.

The original appearance of the primitive

OSERDESE2 #(
      .DATA_RATE_OQ("DDR"), // DDR, SDR
      .DATA_RATE_TQ("DDR"), // DDR, BUF, SDR
      .DATA_WIDTH(4), // Parallel data width (2-8,10,14)
      .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
      .INIT_TQ(1'b0), // Initial value of TQ output (1'b0,1'b1)
      .SERDES_MODE("MASTER"), // MASTER, SLAVE
      .SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
      .SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)
      .TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
      .TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
      .TRISTATE_WIDTH(4) // 3-state converter width (1,4)
   )
   OSERDESE2_inst (
      .OFB(OFB), // 1-bit output: Feedback path for data
      .OQ(OQ), // 1-bit output: Data path output
      // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
      .SHIFTOUT1(SHIFTOUT1),
      .SHIFTOUT2(SHIFTOUT2),
      .TBYTEOUT(TBYTEOUT), // 1-bit output: Byte group tristate
      .TFB(TFB), // 1-bit output: 3-state control
      .TQ(TQ), // 1-bit output: 3-state control
      .CLK(CLK), // 1-bit input: High speed clock
      .CLKDIV(CLKDIV), // 1-bit input: Divided clock
      // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
      .D1(D1),
      .D2(D2),
      .D3(D3),
      .D4(D4),
      .D5(D5),
      .D6(D6),
      .D7(D7),
      .D8(D8),
      .OCE(OCE), // 1-bit input: Output data clock enable
      .RST(RST), // 1-bit input: Reset
      // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
      .SHIFTIN1(SHIFTIN1),
      .SHIFTIN2(SHIFTIN2),
      // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
      .T1(T1),
      .T2(T2),
      .T3(T3),
      .T4(T4),
      .TBYTEIN(TBYTEIN), // 1-bit input: Byte group tristate
      .TCE(TCE) // 1-bit input: 3-state clock enable
   );

HDMI usage primitives

module par_to_ser(
    input wire sys_clk,
    input wire sys_clk_5x ,
    input wire sys_rst_n ,
    input wire [9:0] data_in ,
    output wire data_p,
    output wire data_n
    );

    
wire shift_data1;
wire shift_data2;

wire data;

 OSERDESE2 #(
      .DATA_RATE_OQ("DDR"), // DDR, SDR
      .DATA_RATE_TQ("DDR"), // DDR, BUF, SDR
      .DATA_WIDTH(10), // Parallel data width (2-8,10,14)
      .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
      .INIT_TQ(1'b0), // Initial value of TQ output (1'b0,1'b1)
      .SERDES_MODE("MASTER"), // MASTER, SLAVE
      .SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
      .SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)
      .TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
      .TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
      .TRISTATE_WIDTH(1) // 3-state converter width (1,4)
   )
   OSERDESE2_inst1 (
      .OFB(), // 1-bit output: Feedback path for data
      .OQ(data), // 1-bit output: Data path output
      // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
      .SHIFTOUT1(),
      .SHIFTOUT2(),
      .TBYTEOUT(), // 1-bit output: Byte group tristate
      .TFB(), // 1-bit output: 3-state control
      .TQ(), // 1-bit output: 3-state control
      .CLK(sys_clk_5x), // 1-bit input: High speed clock
      .CLKDIV(sys_clk), // 1-bit input: Divided clock
      // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
      .D1(data_in[0]),
      .D2(data_in[1]),
      .D3(data_in[2]),
      .D4(data_in[3]),
      .D5(data_in[4]),
      .D6(data_in[5]),
      .D7(data_in[6]),
      .D8(data_in[7]),
      .OCE(1), // 1-bit input: Output data clock enable
      .RST(~sys_rst_n), // 1-bit input: Reset
      // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
      .SHIFTIN1(shift_data1),
      .SHIFTIN2(shift_data2),
      // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
      .T1(0),
      .T2(0),
      .T3(0),
      .T4(0),
      .TBYTEIN(0), // 1-bit input: Byte group tristate
      .TCE(0) // 1-bit input: 3-state clock enable
   );
   
OSERDESE2 #(
      .DATA_RATE_OQ("DDR"), // DDR, SDR
      .DATA_RATE_TQ("DDR"), // DDR, BUF, SDR
      .DATA_WIDTH(10), // Parallel data width (2-8,10,14)
      .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
      .INIT_TQ(1'b0), // Initial value of TQ output (1'b0,1'b1)
      .SERDES_MODE("SLAVE"), // MASTER, SLAVE
      .SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
      .SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)
      .TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
      .TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
      .TRISTATE_WIDTH(1) // 3-state converter width (1,4)
   )
   OSERDESE2_inst2 (
      .OFB(), // 1-bit output: Feedback path for data
      .OQ(), // 1-bit output: Data path output
      // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
      .SHIFTOUT1(shift_data1),
      .SHIFTOUT2(shift_data2),
      .TBYTEOUT(), // 1-bit output: Byte group tristate
      .TFB(), // 1-bit output: 3-state control
      .TQ(), // 1-bit output: 3-state control
      .CLK(sys_clk_5x), // 1-bit input: High speed clock
      .CLKDIV(sys_clk), // 1-bit input: Divided clock
      // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
      .D1(0),
      .D2(0),
      .D3(data_in[8]),
      .D4(data_in[9]),
      .D5(0),
      .D6(0),
      .D7(0),
      .D8(0),
      .OCE(1), // 1-bit input: Output data clock enable
      .RST(~sys_rst_n), // 1-bit input: Reset
      // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
      .SHIFTIN1(),
      .SHIFTIN2(),
      // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
      .T1(0),
      .T2(0),
      .T3(0),
      .T4(0),
      .TBYTEIN(0), // 1-bit input: Byte group tristate
      .TCE(0) // 1-bit input: 3-state clock enable
   );
   
OBUFDS #(
      .IOSTANDARD("TMDS33"), // Specify the output I/O standard
      .SLEW("SLOW") // Specify the output slew rate
   ) OBUFDS_inst (
      .O (data_p), // Diff_p output (connect directly to top-level port)
      .OB(data_n), // Diff_n output (connect directly to top-level port)
      .I(data) // Buffer input
   );
endmodule