Table of Contents
Serial port reception (RX)
Serial port transmission (TX)
Serial communication module
Serial port reception (RX)
`timescale 1ns / 1ps
module UART_RX(
inputclk,
input rst_n,
input rx,
output rx_done ,
output [7:0] rx_data
);
//parameter hz=50_00;
//parameter bps = 96;
parameter hz=50_000_000;
parameter bps = 9600;
parameter delay = hz/bps;
wire rd_en;
reg en;
reg [31:0] cnt;
reg [5:0] cnt_bit;
reg [7:0] data_reg;
reg rx1;
reg rx2;
always @(posedge clk)
if(!rst_n)begin
rx1<=0;
rx2<=1;
end
else begin
rx1<=rx;
rx2<=rx1;
end
assign rd_en = (~rx1 & amp; & amp;rx2) ?1:0; //When rx1 is 0 and rx2 is 1, rd_en == 1
//en is used to determine whether data is being received. When en == 1, it is received.
always @(posedge clk)
if(!rst_n)
en<=0;
else if(rd_en)
en<=1;
else if(cnt_bit == 9 & amp; & amp; cnt == delay/2-1)
en<=0;
else
en<=en;
always @(posedge clk)
if(!rst_n)begin
cnt<=0;
cnt_bit<=0;
end
else if(en)begin
if(cnt == delay -1)begin
cnt <= 0;
cnt_bit <= cnt_bit + 1;
end
else begin
cnt <=cnt + 1;
cnt_bit <=cnt_bit;
end
end
else begin
cnt<=0;
cnt_bit <=0;
end
always @(posedge clk)
if(!rst_n)begin
data_reg<=0;
end
else if(cnt_bit >0 & amp; & amp; cnt_bit <9 & amp; & amp; cnt == delay/2-1)
data_reg [cnt_bit -1] = rx;
else begin
data_reg<=data_reg;
end
//update data
assign rx_data = (cnt_bit ==9) ?data_reg:rx_data;
//Send end signal
assign rx_done = (cnt_bit ==9 & amp; & amp; cnt == delay /2-1)?1:0;
endmodule
-
Clock and reset module:
timescale 1ns / 1ps: Set the time scale to 1 nanosecond / 1 picosecond.clk: Input clock signal.rst_n: Reset signal, active low level.rx: Input UART serial data bits.rx_done: Output signal, indicating that complete data has been received.rx_data: Output signal, indicating received data.
-
Parameter module:
hz: clock frequency, default is 50 MHz.bps: UART communication baud rate, the default is 9600.
-
Clock cycle calculation module:
delay: Calculate the number of clock cycles required to receive a complete serial data bit, that is, the clock frequency divided by the baud rate.
-
Data receiving module:
rd_en: A signal to determine whether to start receiving data. When the received data in the previous clock cycle is 0 and the received data in the current clock cycle is 1, it indicates that data reception has started.en: Receive enable signal. When rd_en is 1, it means starting to receive data.cnt: A register that counts clock cycles.cnt_bit: A register that counts the number of data bits received.data_reg: A register that stores received data.rx1andrx2: store the received data of the previous and current clock cycle.
-
Receiving status control module:
- The transition of the receive state is controlled by the always block triggered by the clock edge.
- According to the values of the reset signal and rd_en signal, the conversion of the en signal is controlled to determine whether to start receiving data or to end receiving data.
- According to the reset signal, en signal and the value of the counting register, the conversion of the cnt and cnt_bit registers is controlled to realize the counting function.
-
Data storage module:
- Received data is stored via a clock edge triggered always block.
- According to the values of the reset signal, the count register and the received data, the received data is stored in the corresponding location of the data_reg register.
-
Output module:
- Update the rx_data signal through the assign statement, determine whether a complete byte of data is received based on the value of the counting register, and assign the value of data_reg to rx_data.
- Update the rx_done signal through the assign statement, and determine whether the reception is completed based on the counting register and the calculated delay value. When the number of received digits is 9 and the count value is delay/2-1, rx_done is set to 1, indicating that the reception is completed.
Receive UART serial data and store the received data in rx_data. When the reception is completed, set rx_done to 1. Counters and state machines are designed to control the timing of receiving data and state transitions.
Serial port transmission (TX)
`timescale 1ns / 1ps
module UART_TX(
inputclk,
input rst_n ,
input rx_done,
input [7:0] rx_data , //Receive data in parallel
output reg tx , //data output
output tx_done //module end signal
);
//parameter HZ = 50_00; //1s time
//parameter bps = 96; //Baud rate
parameter HZ = 50_000_000; //1s time
parameter bps = 9600; //Baud rate
parameter delay = HZ/bps; //The number of clock cycles required for 1bit
reg [31:0] cnt;
reg [5:0] cnt_bit;
reg en;
always @(posedge clk)
if(!rst_n)
en <= 0;
else if (rx_done)
en<=1;
else if(cnt == delay /2 -1 & amp; & amp; cnt_bit == 9)
en<=0;
else
en<=en;
always @(posedge clk)
if(!rst_n) begin
cnt <= 0;
cnt_bit <= 0;
end
else if (en)begin
if(cnt == delay -1)begin
cnt <= 0;
cnt_bit <= cnt_bit + 1;
end
else begin
cnt <= cnt + 1;
cnt_bit <= cnt_bit;
end
end
else begin
cnt <= 0;
cnt_bit <= 0;
end
always @(posedge clk)
if(!rst_n) begin
tx <= 1;
end
else if (cnt_bit ==0 & amp; & amp; en == 1 )begin
tx <=0;
end
else if (cnt_bit > 0 & amp; & amp; cnt_bit <9)begin
tx <=rx_data[cnt_bit -1];
end
else begin
tx <= 1;
end
assign tx_done = (cnt_bit == 9 & amp; & amp; cnt_bit == delay/2-1) ?1:0;
endmodule
-
Clock and reset module:
timescale 1ns / 1ps: Set the time scale to 1 nanosecond / 1 picosecond.clk: Input clock signal.rst_n: Reset signal, active low level.rx_done: Input signal, indicating the completion of reception.rx_data: Input signal, indicating the data to be sent.
-
Parameter module:
HZ: clock frequency, default is 50 MHz.bps: UART communication baud rate, the default is 9600.
-
Clock cycle calculation module:
delay: Calculate the number of clock cycles required to send a complete serial data bit, that is, the clock frequency divided by the baud rate.
-
Send status control module:
en: Send the enable signal, and determine whether to start sending data based on the value of the reception completion signal rx_done.cnt: A register that counts clock cycles.cnt_bit: A register that counts the number of data bits sent.
-
Data sending module:
- The data sending status and timing are controlled through the always block triggered by the clock edge.
- According to the values of the reset signal and the reception completion signal, the conversion of the en signal is controlled,
Serial communication module
`timescale 1ns / 1ps
module uart_1(
inputclk,
input rst_n ,
input rx,
output tx //data output
);
wire rx_done;
wire [7:0] rx_data;
wire tx_done;
UART_RX r(
.clk(clk),
.rst_n (rst_n),
. rx ( rx ),
. rx_done ( rx_done ),
. rx_data ( rx_data )
);
UART_TX t(
.clk(clk),
.rst_n (rst_n),
. rx_done ( rx_done ) ,
. rx_data (rx_data), //Receive data in parallel
.tx (tx), //data output
.tx_done (tx_done) //Module end signal
);
endmodule
Interconnect the information received and sent by the serial port, and transmit the received information.