FPGA—— Ultrasonic module based on ZYNQ ECO development board

Table of Contents

Ultrasonic module

led

Ultrasonic ranging


ultrasonic module

`timescale 1ns / 1ps
module SR_04(
        inputclk,
        input rst_n ,
        input echo, //receiving end, determine the port return value
        output [15:0] dis , //final distance
        output trig //pulse is emitted
    );
    
    parameter delay = (50*15) + (50*1000*100); //Period above 60ms
    parameter s1 = 0; //idle
    parameter s2 = 1; //echo starts timing
    parameter s3 = 2; //Timeout ends
    
    reg [31:0] cnt_trig;
    reg [31:0] cnt_echo;
    reg [31:0] cnt_echo_reg;
    reg [2:0] c_state;
    reg [2:0] n_state;
    
    
    always @(posedge clk)
        if(!rst_n)
            cnt_trig <= 0;
        else if(cnt_trig == delay -1)
            cnt_trig <= 0;
        else
            cnt_trig <= cnt_trig + 1
            ;
    assign trig = ((cnt_trig >0) & amp; & amp; (cnt_trig<(50*15))) ? 1:0;
    
    
    always @(posedge clk)
        if(!rst_n)
            c_state <= s1;
        else
            c_state <= n_state;
            
     always @(*)
        case(c_state)
            s1: begin
                if(echo == 1)
                    n_state = s2;
                else
                    n_state = s1;
                 end
            s2: begin
                if(echo == 0)
                    n_state = s3;
                else
                    n_state = s2;
            end
            s3: begin
                n_state = s1;
             end
         endcase
    
    
always @(posedge clk)
    if(!rst_n)begin
        cnt_echo<=0;
        cnt_echo_reg <= 0;
    end
    else begin
            case(c_state)
                s1: begin
                    cnt_echo<=0;
                    cnt_echo_reg <= cnt_echo_reg;
                    end
                s2: begin
                    cnt_echo<=cnt_echo + 1;
                    cnt_echo_reg <= cnt_echo_reg;
                   end
                s3: begin
                    cnt_echo<=cnt_echo;
                    cnt_echo_reg <= cnt_echo;
                    end
            endcase
     end
        
        
assign dis = (cnt_echo_reg * 20)/1000/58;

endmodule

The input of the module includes clock signal clk, reset signal rst_n, and echo signal (receiver return value); the output includes distance signal dis and pulse signal trig.

This module defines some parameters and registers for tracking counts. The delay parameter defines the delay time of the cycle. s1, s2 and s3 represent the three states of the state machine respectively. .

In the always block triggered by the rising edge of the clock signal, the value of the counter cnt_trig is set according to the state of the reset signal. When cnt_trig reaches delay-1, reset it to 0. Set the trig output to 1 or 0 based on the value of cnt_trig to control pulse emission.

In another always block triggered by the rising edge of the clock signal, the values of the counters cnt_echo and cnt_echo_reg are set according to the reset signal and the current state of the state machine. Depending on the state of the state machine, the value of cnt_echo will be incremented or remain unchanged. cnt_echo_reg saves the counter value of the previous state.

Finally, through combinational logic, cnt_echo_reg is multiplied by 20, divided by 1000, and then divided by 58 to obtain the distance value dis.

The function of this ultrasonic module is to implement ultrasonic ranging through a counter. It measures the time from transmission to reception of ultrasonic waves, and then converts the time into a distance value. Equivalent to the ultrasonic distance we can get elsewhere.

The output dis unit is cm

LED

`timescale 1ns / 1ps

module led_mk(
    inputclk,
    input rst_n ,
    input [4:0] led_zt ,
    output reg[3:0] led
    );
    parameter led1 = 0;
    parameter led2 = 1;
    parameter led3 = 2;
    parameter led4 = 3;
    parameter led5 = 4;
    
    reg [3:0] c_led;
    reg [3:0] n_led;
    
    always @(posedge clk)
        if(!rst_n)
            c_led <= led1;
        else
            c_led <= n_led;
        
    always @(*)
        if(!rst_n)
            n_led = 0;
        else begin
            case(led_zt)
                led1: begin
                    n_led = led1;
                    end
                led2:begin
                     n_led = led2;
                    end
                led3:begin
                     n_led = led3;
                    end
                led4:begin
                     n_led = led4;
                    end
                led5:begin
                     n_led = led5;
                    end
                default:
                    n_led = n_led;
              endcase
        end
                
       always @(posedge clk)
            if(!rst_n)
                led <= 0;
            else begin
                case(c_led)
                led1: begin
                        led <= 4'b0000;
                    end
                led2:begin
                        led <= 4'b0001;
                    end
                led3:begin
                        led <= 4'b0011;
                    end
                led4:begin
                        led <= 4'b0111;
                    end
                led5:begin
                        led <= 4'b1111;
                    end
                default:
                    led <= led;
                 endcase
            end
endmodule

Here, the status of ed display is controlled by the input led_zt.

Ultrasonic ranging

`timescale 1ns / 1ps
module sr_led(
        inputclk,
        input rst_n ,
        input echo, //receiving end, determine the port return value
        output trig, //pulse is emitted
        output reg [3:0] led
    );
    wire [15:0] dis;
    wire [3:0] led_dd;
    reg [4:0] led_zt;
    
    always @(posedge clk)
        if(!rst_n) begin
            led <= 0;
            end
        else
            led <= led_dd;
            
    parameter csb0 = 0;
    parameter csb1 = 2;
    parameter csb2 = 4;
    parameter csb3 = 6;
    parameter csb4 = 8;
    
    always @(posedge clk)
        if(!rst_n)
            led_zt <= 0;
        else if (dis > csb4 )
            led_zt <= 4;
        else if (dis > csb3 & amp; & amp; dis <= csb4)
            led_zt <= 3;
        else if (dis > csb2 & amp; & amp; dis <= csb3)
            led_zt <= 2;
        else if (dis > csb1 & amp; & amp; dis <= csb2)
            led_zt <= 1;
        else if (dis > csb0 & amp; & amp; dis <= csb1)
            led_zt <= 0;
            
    
led_mk kk(
    .clk (clk) ,
    .rst_n (rst_n) ,
    . led_zt (led_zt) ,
    . led (led_dd)
    );
    
SR_04 sr(
        .clk (clk) ,
        .rst_n (rst_n) ,
        . echo (echo), //receiving end, determine the port return value
        . dis (dis) , //final distance
        . trig (trig) //Pulse is emitted
    );
endmodule

Control the LED status by calling l ultrasonic distance