2. Sequential Logic sequential logic circuit
2.1 Latches and Flip-Flops latches and flip-flops
2.1.1 D filp-flop [Dff]
Problem description
A D flip-flop is a circuit that stores 1 bit and updates it periodically on the (usually) rising edge of a clock signal.
When D flip-flops are created by a logic synthesizer, the always block is usually used. The D flip-flop is the simplest form of “combinational logic followed by a flip-flop”, where the combinational logic part is just a wire.
(I can’t understand the machine translation myself – -, the original text is as follows: D flip-flops are created by the logic synthesizer when a clocked always block is used. A D flip-flop is the simplest form of “blob of combinational logic followed by a flip-flop” where the combinational logic portion is just a wire. )
Code
module top_module (
input clk, // Clocks are used in sequential circuits
input d,
output reg q );//
\t
always@(posedge clk) begin
q<=d;
end
// Use a clocked always block
// copy d to q at every positive edge of clk
// Clocked always blocks should use non-blocking assignments
endmodule
2.1.2 D filp-flops [Dff8]
Problem description
Create an 8-bit D flip-flop, all flip-flops should be triggered by the rising edge of clk.
Code
module top_module (
input clk,
input [7:0] d,
output [7:0] q
);
always@(posedge clk) begin
q <= d;
end
endmodule
2.1.3 DFF with reset [Dff8r]
Problem description
Build an 8-bit D flip-flop with high level synchronous reset, all flip-flops should be triggered by clk rising edge.
Code
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output [7:0] q
);
always@(posedge clk) begin
if (reset == 1)
q <= 8'd0;
else
q <= d;
end
endmodule
2.1.4 DFF with reset value [Dff8p]
Problem description
Create an 8-bit flip-flop with a high-level synchronous reset. The flip-flop reset should be set to 0x34 instead of 0. All D flip-flops are triggered by a falling edge.
Code
module top_module (
input clk,
input reset,
input [7:0] d,
output [7:0] q
);
always@(negedge clk) begin
if(reset==1)
q <= 8'h34;
else
q <= d;
end
endmodule
2.1.5 DFF with asynchronous reset [Dff8ar]
Problem description
Create a high-level asynchronous reset 8-bit D flip-flop. All D flip-flops are triggered by the rising edge of clk.
Code
module top_module (
input clk,
input areset, // active high asynchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk or posedge areset) begin
if(areset == 1)
q <= 8'd0;
else
q <= d;
end
endmodule
2.1.6 DFF with byte enable [Dff16e]
Problem description
Create a 16-bit D flip-flop. Sometimes it is useful to modify only part of a set of triggers. The byte enable input controls whether each byte of the 16 registers is written during this cycle. Byteena[1] controls the high bits d[15:8], byteena[0] controls the low bits d[7:0], and there is a synchronous low-level active reset.
All flip-flops are valid on the rising edge of clk.
Code
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output [15:0] q
);
always @(posedge clk) begin
if (resetn == 0)
q <= 16'd0;
else begin
case(byteena)
2'b00: q <= q;
2'b01 : q[7:0] <= d[7:0];
2'b10 : q[15:8] <= d[15:8];
2'b11 : q <= d;
endcase
end
end
endmodule
The main thing is to clearly write down the various situations of the enabling end, and it should be enough to make sure there are no missing items. The four situations of byteena are clearly written, but default is not written.
2.1.7 D Latch [Exams/m2014 q4a]
Problem description
Implement the circuit below
Note that this is a latch, so Quartus will give a warning about inferring the latch
Note
- Latches are level-sensitive (not edge-sensitive) circuits, so use a level-sensitive list in the always block.
- However, they are still sequential elements, so non-blocking assignments should be used.
- A D latch acts like a wire (or non-inverted buffer) when enabled and holds its current value when disabled.
Code
module top_module (
input d,
input ena,
output q);
always @(ena) begin
if(ena == 1)
q <= d;
else
q <= q;
end
endmodule
2.1.8 DFF [Exams/m2014 q4b]
Problem description
Complete the circuit below:
Analysis
According to the picture, the DFF should be a 1-bit D flip-flop, rising edge triggered, and have an asynchronous reset.
Mainly asynchronous reset and synchronous reset
Code
module top_module (
input clk,
input d,
input ar, // asynchronous reset
output q);
always @(posedge clk or posedge ar) begin
if(ar == 1)
q <= 0;
else
q <= d;
end
endmodule
2.1.9 DFF [Exams/m2014 q4c]
Problem description
Complete the circuit below:
Analysis
Similar to the previous question, only changed to synchronous reset.
Code
module top_module (
input clk,
input d,
input r, // synchronous reset
output q);
always @(posedge clk) begin
if(r)
q <= 1'b0;
else
q <= d;
end
endmodule
Note: In Quartus II13.1, the variable output q should be set to output reg q.
The specific error is: object "q" on left-hand side of assignment must have a variable data type
2.1.10 DFF + gate [Exams/m2014 q4d]
Problem description
Complete the circuit below:
Analysis
The input of the D flip-flop is the output after the XOR gate of the in and out inputs. Just write it directly. Note that it is triggered by the rising edge of clk.
Code
module top_module (
input clk,
input in,
output out);
always@(posedge clk) begin
out <= in ^ out;
end
endmodule
2.1.11 Mux and DFF [Mt2015 muxdff]
Problem description
Complete the circuit below:
Suppose you want to implement hierarchical Verilog code for this circuit, using the example of three submodules containing flip-flops and multiplexers. Write a Verilog module called top_module (containing a flip-flop and multiplexer) for this submodule.
Tips
Note that the sub-module is written, including a flip-flop and a 2-to-1 option, as shown in the figure below.
Code
module top_module (
input clk,
input L,
input r_in,
input q_in,
output reg Q);
wire mux_out;
assign mux_out = L ? r_in : q_in;
always@(posedge clk) begin
Q <= mux_out;
end
endmodule
2.1.12 Mux and DFF [Exams/2014 q4a]
Problem description
Complete the n-bit shift register circuit as shown below:
Write a Verilog module called top_module for this circuit, containing flip-flops and multiplexers
Analysis
Write a small module of it
Code
module top_module (
input clk,
input w, R, E, L,
outputQ
);
wire mux_out1,mux_out2;
assign mux_out1 = E ? w : Q;
assign mux_out2 = L ? R : mux_out1;
always@(posedge clk) begin
Q <= mux_out2;
end
endmodule
2.1.13 DFFs and gates [Exams/ece241 2014 q4]
Problem description
Given the finite state machine circuit shown in the figure below, assume that the D flip-flop is initially reset to 0 before starting.
Build this circuit.
Analysis
Mark some lines that need to be defined, as shown in the figure below
Code
module top_module (
input clk,
input x,
output z
);
reg q1,q2,q3;
wire xor_out,and_out,or_out;
assign xor_out = x ^ q1;
assign and_out = x & amp; ~q2;
assign or_out = x | ~q3;
always @(posedge clk) begin
q1 <= xor_out;
q2 <= and_out;
q3 <= or_out;
end
assign z = ~ (q1 | q2 | q3);
endmodule
Pay attention to the picture carefully, there is a NOR gate at the end! ! (〃＞ dishes＜) Abominable.
2.1.14 create circuit from truth table [Exams/ece241 2013 q7]
Problem description
A JK flip-flop has the following truth table. To implement a JK flip-flop, there is only a D-type flip-flop and gate circuit. Note: Qold is the output of the D flip-flop before the rising edge.
Analysis
The JK flip-flop status is as follows, just follow the implementation.
| J | K | Q n | Qn + 1 |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 0 |
Draw a Karnaugh map to get:
Simplify to get
Q
n
+
1
=
j
Q
‘
+
k
‘
Q
Q_{n + 1} = jQ’ + k’Q
Qn + 1?=jQ′ + k′Q
Code
module top_module (
input clk,
input j,
input k,
outputQ);
always @(posedge clk) begin
Q <= (j & amp; ~Q)|(~k & amp; Q);
end
endmodule
2.1.15 Detect an edge [Edgedetect]
Problem description
For each bit in an 8-bit vector, detect when the input signal changes from 0 in one clock cycle to 1 in the next clock cycle (similar to rising edge detection ). The output bit should be set one cycle after a 0 to 1 transition occurs.
The following is an example. For clear analysis, in[1] and edge[1] are listed separately.
Analysis
First, comparing in and clk, we can see that this circuit is a rising edge active module, in which the change of edge is delayed by in one clock cycle. To determine whether there is an edge change, you can store the previous state in a register, then compare the current state to determine whether there is an edge change, and obtain the state of the rising edge. The method is to use AND to compare the current state with the previous state to ensure the current state. It should be 1, the previous state is 0, and the result is a rising edge.
Code
module top_module (
input clk,
input [7:0] in,
output [7:0] page
);
reg [7:0] temp;
always@(posedge clk) begin
temp <= in;
pedge <= in & amp; ~temp;
end
endmodule
2.1.16 Detect both edges [Edgedetect2]
Problem description
For each bit in an 8-bit vector, detect when the input signal changes from one clock cycle to the next (detect any edge). The output bit should be set one cycle after a 0/1 transition occurs.
The following is an example. For clear analysis, in[1] and edge[1] are listed separately.
Analysis
It is still an upper edge triggered circuit, but this time the output result is to detect both edges 0->1 and 1->0. Combined with the experience of the previous question, you can directly use the XOR relationship to complete the circuit design.
Code
module top_module (
input clk,
input [7:0] in,
output [7:0] anyedge
);
reg [7:0] temp;
always@(posedge clk) begin
temp <= in;
anyedge <= temp ^ in;
end
endmodule
2.1.17 Edge capture register [Edgecapture]
Problem description
For each bit in a 32-bit vector, capture when the input signal changes from 1 on one clock cycle to 0 on the next clock cycle (falling edge detection). “Capture” means that the output remains at 1 without reset.
Each output bit behaves like an SR flip-flop: the output bit should be set to 1 in the period after a 1 to 0 transition occurs. When reset is high, the output bit should be reset to 0 on the rising edge. If the above two events occur at the same time, the reset event takes precedence. In the last four cycles of the example waveform below, the reset event occurs one cycle before the set event, so there is no conflict.
In the example waveform below, reset, in[1] and out[1] are shown separately for clarity.
Code
module top_module (
input clk,
input reset,
input [31:0] in,
output [31:0] out
);
reg [31:0] temp;
always@(posedge clk) begin
temp <= in;
if(reset==1)
out <= 0;
else
out <= temp & amp; ~in | out;
end
endmodule
The main thing to note is that in the absence of reset, the output bits set to 1 will remain unchanged. Here, |out is used to maintain the capture state. At the same time, according to the timing diagram, it can be seen that it is a synchronous reset circuit, and the high level resets the bit to zero.
2.1.18 Dual-edge triggered flip-flop [Dualedge]
Problem description
You are familiar with flip-flops that fire on the rising edge of a clock, or on the falling edge of a clock. The dual-edge flip-flop is triggered on the upper and lower edges of the clock at the same time. However, FPGAs do not have dual edge triggers, and always@(posedge clk or negedge clk) is not a legal sensitivity list.
Build a circuit that functions like a dual-edge flip-flop.
Analysis
It can be split into two edge flip-flops respectively, and then the results of the two edge flip-flops are used as the previous output state of the other edge flip-flop. Compare the two output states before and after. If there is a change, 1 is output. You can use XOR here. relationship to express. For the output results of the two edge flip-flops, do another XOR operation to get the final result of q<=d.
At rising edge qup <= d ^ qdown; q <= qup ^ qdown (=d);
At falling edge qdown <= d ^ qup; q <= qdown ^ qup (=d);
Code
module top_module (
input clk,
input d,
output q
);
reg qup,qdown;
always @(posedge clk) begin
qup <= d ^ qdown;
end
\t
always @(negedge clk) begin
qdown <= d ^ qup;
end
\t
assign q = qup ^ qdown;
endmodule
This series mainly records my own learning process and simple thinking process, and also refers to many other people’s ideas. The title and some pictures are quoted from the original title and pictures on HDLBits, and are simply organized with the help of a translator and my own understanding. Check out the language. If there are any questions, you are welcome to criticize and correct me.