1. What is asynchronous FIFO Asynchronous FIFO is one of the FIFO designs (First In First Out, data written first is read out first). Since read and write operations are independent, asynchronous FIFO is often used to transmit multi-bit data across clock domains. Asynchronous FIFO will be referred to as FIFO in the following. Under […]
Tag: hdl
[HDLBits question] Sequential Logic — Finite State Machines (III)
(Continued from 2.5Finite State Machine(II)) 2.5.24 Q3a:FSM [Exams/2014 q3fsm] Problem description Consider a finite state machine with inputs s and w. Assume that the FSM starts from a reset state called A, as shown below, the FSM remains in state A as long as s=0, and when s=1, the A state transitions to the B […]
[HDLBits question] Sequential Logic — Finite State Machines (II)
There were too many chores during the week, so I found an excuse to do some homework on the weekend. As a result, after watching the game over the weekend, the Dalian team was relegated. I was very sad and found an excuse not to do the questions. Well, it’s been a decadent week, so […]
hdlbits->circuits->sequential logic->latches and flip-flps
Dff A D flip-flop is a circuit that stores a bit and is updated periodically, at the (usually) positive edge of a clock signal. D flip-flops are created by the logic synthesizer when a clocked always block is used (See alwaysblock2). A D flip-flop is the simplest form of “blob of combinational logic followed by […]
[HDLBits question] Sequential Logic — Finite State Machines (I)
2.5 Finite State Machines Finite State Machine (1) 2.5.1 Simple FSM 1(asynchronous reset) [Fsm1] Problem description The picture below is a Moore state machine with two states, one input and one output. Use the circuit to implement this state machine, and the asynchronous reset state is set to the B state. Tips This is an […]
Quickly implement systolic FIR filter based on FPGA, VHDL, systolic array, PE processing unit, FIR filter
Click the blue words to follow us Follow and star the public account, and exciting content will be delivered every day Source: Internet material At present, most methods of implementing FIR (Finite Impulse Response) filters using FPGA (Field Programmable Gate Array) take advantage of the characteristics of the LUT (Lookup Table) in the FPGA and […]
[HDLBits question] Sequential Logic — Shift Registers
2.3 Shift Registers shift register 2.3.1 4-bit shift register [Shift4] Problem description Build a 4-bit shift register (shift right) with synchronous reset, synchronous read and enable. areset : The shift register is reset to 0. load: Load the shift register with data[3:0] instead of shifting. ena : Shift to the right (q[3] becomes 0, q[0] […]
[HDLBits question] Sequential Logic — Counters
2.2 Counters Counters 2.2.1 Four-bit binary counter [Count15] Problem description Create a 4-bit binary counter that counts from 0 to 15, with a period of 16 and a synchronous reset bit of 0. Analysis According to the timing diagram, it can be seen that the counter counts increment by one on the rising edge. There […]
HDL implementation of mean filter algorithm for grayscale images
Click the blue words to follow us Follow and star the public account, and exciting content will be delivered every day Source: Internet material 1.1 Introduction to mean filter algorithm The first thing to do is the simplest mean filter algorithm. Mean filtering is a typical linear filtering algorithm. It refers to giving a template […]
[HDLBits question] Sequential Logic — Latches and Flip-Flops
2. Sequential Logic sequential logic circuit 2.1 Latches and Flip-Flops latches and flip-flops 2.1.1 D filp-flop [Dff] Problem description A D flip-flop is a circuit that stores 1 bit and updates it periodically on the (usually) rising edge of a clock signal. When D flip-flops are created by a logic synthesizer, the always block is […]