Dff
A D flip-flop is a circuit that stores a bit and is updated periodically, at the (usually) positive edge of a clock signal.
D flip-flops are created by the logic synthesizer when a clocked always block is used (See alwaysblock2). A D flip-flop is the simplest form of “blob of combinational logic followed by a flip-flop” where the combinational logic portion is just a wire.
Create a single D flip-flop.
Module Declaration
module top_module (
input clk, // Clocks are used in sequential circuits
input d,
output reg q );
Write your solution here
module top_module (
input clk, // Clocks are used in sequential circuits
input d,
output reg q );//
// Use a clocked always block
// copy d to q at every positive edge of clk
// Clocked always blocks should use non-blocking assignments
always@(posedge clk) begin
q <= d;
end
endmodule
Web answer:
module top_module( input clk, input d, output reg q); \t // Use non-blocking assignment for edge-triggered always blocks always @(posedge clk) q <= d; // Undefined simulation behavior can occur if there is more than one edge-triggered // always block and blocking assignment is used. Which always block is simulated first? \t endmodule
Dff8
Create 8 D flip-flops. All DFFs should be triggered by the positive edge of clk.
Module Declaration
module top_module (
input clk,
input [7:0] d,
output [7:0] q
);
Write your solution here
module top_module (
input clk,
input [7:0] d,
output [7:0] q
);
always@(posedge clk) begin
q <= d;
end
endmodule
Web answer:
module top_module( input clk, input [7:0] d, output reg [7:0] q); \t // Because q is a vector, this creates multiple DFFs. always @(posedge clk) q <= d; \t endmodule
Dff8r
Create 8 D flip-flops with active high synchronous reset. All DFFs should be triggered by the positive edge of clk.
Module Declaration
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output [7:0] q
);
Write your solution here
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output [7:0] q
);
always@(posedge clk) begin
if (reset)
q <= 0;
else
q <= d;
end
endmodule
Dff8p
Create 8 D flip-flops with active high synchronous reset. The flip-flops must be reset to 0x34 rather than zero. All DFFs should be triggered by the negative edge of clk.
Module Declaration
module top_module (
input clk,
input reset,
input [7:0] d,
output [7:0] q
);
Hint…
Resetting a register to ‘1’ is sometimes called “preset”
Write your solution here
module top_module (
input clk,
input reset,
input [7:0] d,
output [7:0] q
);
always@(negedge clk) begin
if (reset) begin
q <= 8'h34;
end
else begin
q <= d;
end
end
endmodule
Dff8ar
Create 8 D flip-flops with active high asynchronous reset. All DFFs should be triggered by the positive edge of clk.
Module Declaration
module top_module (
input clk,
input areset, // active high asynchronous reset
input [7:0] d,
output [7:0] q
);
Hint…
The only difference in code between synchronous and asynchronous reset flip-flops is in the sensitivity list.
Write your solution here
module top_module (
input clk,
input areset, // active high asynchronous reset
input [7:0] d,
output [7:0] q
);
always@(posedge clk or posedge areset) begin
if(areset) begin
q <= 0;
end
else begin
q <= d;
end
end
endmodule
Web answer:
module top_module( input clk, input [7:0] d, input areas, output reg [7:0] q); \t // The only difference in code compared to synchronous reset is in the sensitivity list. always @(posedge clk, posedge areset) if(areset) q <= 0; else q <= d; // In Verilog, the sensitivity list looks strange. The FF's reset is sensitive to the // *level* of areset, so why does using "posedge areset" work? // To see why it works, consider the truth table for all events that change the input // signals, assuming clk and areset do not switch at precisely the same time: \t // clk areset output // x 0->1 q <= 0; (because areset = 1) // x 1->0 no change (always block not triggered) // 0->1 0 q <= d; (not resetting) // 0->1 1 q <= 0; (still resetting, q was 0 before too) // 1->0 x no change (always block not triggered) \t endmodule
Dff16e
Create 16 D flip-flops. It’s sometimes useful to only modify parts of a group of flip-flops. The byte-enable inputs control whether each byte of the 16 registers should be written to on that cycle. byteena[1] controls the upper byte d[15:8], while byteena[0] controls the lower byte d[7:0].
resetn is a synchronous, active-low reset.
All DFFs should be triggered by the positive edge of clk.
Module Declaration
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output [15:0] q
);
Write your solution here
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output [15:0] q
);
always@(posedge clk) begin
if (!resetn) begin
q <= 0;
end
else begin
if (&byteena[1:0]) begin
q <= d;
end
else if (byteena[1]) begin
q[15:8] <= d[15:8];
end
else if (byteena[0]) begin
q[7:0] <= d[7:0];
end
else begin
q <= q;
end
end
end
endmodule
Exams/m2014 q4a
Implement the following circuit:
Note that this is a latch, so a Quartus warning about having inferred a latch is expected.
Module Declaration
module top_module (
input d,
input ena,
output q);
Hint…
- Latches are level-sensitive (not edge-sensitive) circuits, so in an always block, they use level-sensitive sensitivity lists.
- However, they are still sequential elements, so should use non-blocking assignments.
- A D-latch acts like a wire (or non-inverting buffer) when enabled, and preserves the current value when disabled.
Write your solution here
module top_module (
input d,
input ena,
output q);
always@(*)begin
if(ena) begin
q <= d;
end
else begin
q <= q;
end
end
endmodule
Exams/m2014 q4b
Implement the following circuit:
Module Declaration
module top_module (
input clk,
input d,
input ar, // asynchronous reset
output q);
Write your solution here
module top_module (
input clk,
input d,
input ar, // asynchronous reset
output q);
always@(posedge clk or posedge ar) begin
if (ar) begin
q <= 0;
end
else begin
q <= d;
end
end
endmodule
Exams/m2014 q4c
Implement the following circuit:
Module Declaration
module top_module (
input clk,
input d,
input r, // synchronous reset
output q);
Write your solution here
module top_module (
input clk,
input d,
input r, // synchronous reset
output q);
always@(posedge clk) begin
if (r) begin
q <= 0;
end
else begin
q <= d;
end
end
endmodule
Exams/m2014 q4d
Implement the following circuit:
Module Declaration
module top_module (
input clk,
input in,
output out);
Write your solution here
module top_module (
input clk,
input in,
output out);
always@(posedge clk) begin
out <= in ^ out;
end
endmodule
Mt2015 muxdff
Taken from ECE253 2015 midterm question 5
Consider the sequential circuit below:
Assume that you want to implement hierarchical Verilog code for this circuit, using three instantiations of a submodule that has a flip-flop and multiplexer in it. Write a Verilog module (containing one flip-flop and multiplexer) named top_module for this submodule.
Module Declaration
module top_module ( input clk, input L, input r_in, input q_in, output reg Q);
Write your solution here
module top_module (
input clk,
input L,
input r_in,
input q_in,
output reg Q);
always@(posedge clk) begin
Q <= L ? r_in : q_in;
end
endmodule
Exams/2014 q4a
Consider the n-bit shift register circuit shown below:\
Write a Verilog module named top_module for one stage of this circuit, including both the flip-flop and multiplexers.
Module Declaration
module top_module (
input clk,
input w, R, E, L,
outputQ
);
Write your solution here
module top_module (
input clk,
input w, R, E, L,
outputQ
);
always@(posedge clk) begin
Q <= L ? R : (E ? w : Q);
end
endmodule
Exams/ece241 2014 q4
Given the finite state machine circuit as shown, assume that the D flip-flops are initially reset to zero before the machine begins.
Build this circuit.
Module Declaration
module top_module (
input clk,
input x,
output z
);
Hint…
Be careful with the reset state. Ensure that each D flip-flop’s Q output is really the inverse of its Q output, even before the first clock edge of the simulation.
Write your solution here
module top_module (
input clk,
input x,
output z
);
reg d1, d2, d3;
always@(posedge clk) begin
d1 <= x ^ d1;
d2 <= x & amp; ~d2;
d3 <= x | ~d3;
end
assign z = ~(d1 | d2 | d3);
initial z = 1;
endmodule
Exams/ece241 2013 q7
A JK flip-flop has the below truth table. Implement a JK flip-flop with only a D-type flip-flop and gates. Note: Qold is the output of the D flip-flop before the positive clock edge.
Module Declaration
module top_module (
input clk,
input j,
input k,
output Q);
Write your solution here
module top_module (
input clk,
input j,
input k,
outputQ);
always@(posedge clk) begin
Q <= j & amp;~Q | ~k & amp;Q;
end
endmodule
Edgedetect
For each bit in an 8-bit vector, detect when the input signal changes from 0 in one clock cycle to 1 the next (similar to positive edge detection). The output bit should be set the cycle after a 0 to 1 transition occurs.
Here are some examples. For clarity, in[1] and pedge[1] are shown separately.
Module Declaration
module top_module (
input clk,
input [7:0] in,
output [7:0] page
);
Write your solution here
module top_module (
input clk,
input [7:0] in,
output [7:0] page
);
reg [7:0] t1;
always@(posedge clk) begin
t1 <= in;
pedge <= ~t1 & amp;in;
end
endmodule
Web answer:
module top_module( input clk, input [7:0] in, output reg [7:0] page); \t reg [7:0] d_last; \t\t\t always @(posedge clk) begin d_last <= in; // Remember the state of the previous cycle pedge <= in & amp; ~d_last; // A positive edge occurred if input was 0 and is now 1. end \t endmodule
Edgedetect2
For each bit in an 8-bit vector, detect when the input signal changes from one clock cycle to the next (detect any edge). The output bit should be set the cycle after a 0 to 1 transition occurs.
Here are some examples. For clarity, in[1] and anyedge[1] are shown separately
Module Declaration
module top_module (
input clk,
input [7:0] in,
output [7:0] anyedge
);
Write your solution here
module top_module (
input clk,
input [7:0] in,
output [7:0] anyedge
);
reg[7:0]tmp;
always@(posedge clk) begin
tmp <= in;
anyedge <=~tmp & amp;in | tmp & amp;~in;
end
endmodule
Edgecapture
For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. “Capture” means that the output will remain 1 until the register is reset (synchronous reset).
Each output bit behaves like a SR flip-flop: The output bit should be set (to 1) the cycle after a 1 to 0 transition occurs. The output bit should be reset (to 0) at the positive clock edge when reset is high . If both of the above events occur at the same time, reset has precedence. In the last 4 cycles of the example waveform below, the ‘reset’ event occurs one cycle earlier than the ‘set’ event, so there is no conflict here .
In the example waveform below, reset, in[1] and out[1] are shown again separately for clarity.
Module Declaration
module top_module (
input clk,
input reset,
input [31:0] in,
output [31:0] out
);
Write your solution here
module top_module (
input clk,
input reset,
input [31:0] in,
output [31:0] out
);
reg [31:0]tmp;
always@(posedge clk) begin
tmp <= in;
end
always@(posedge clk) begin
if (reset)
out <= 0;
else begin
out <= (~in & amp; tmp) | out;
end
end
endmodule
Dualedge
You’re familiar with flip-flops that are triggered on the positive edge of the clock, or negative edge of the clock. A dual-edge triggered flip-flop is triggered on both edges of the clock. However, FPGAs don’t have dual-edge triggered flip-flops, and always @(posedge clk or negedge clk) is not accepted as a legal sensitivity list.
Build a circuit that functionally behaves like a dual-edge triggered flip-flop:
(Note: It’s not necessarily perfectly equivalent: The output of flip-flops have no glitches, but a larger combinational circuit that emulates this behavior might. But we’ll ignore this detail here.)
Module Declaration
module top_module (
input clk,
input d,
output q
);
Hint…
- You can’t create a dual-edge triggered flip-flop on an FPGA. But you can create both positive-edge triggered and negative-edge triggered flip-flops.
- This problem is a moderately difficult circuit design problem, but requires only basic Verilog language features. (This is a circuit design problem, not a coding problem.) It may help to first sketch a circuit by hand before attempting to code it.
Write your solution here
module top_module (
input clk,
input d,
output q
);
reg pos, neg;
always@(posedge clk)
pos <= d;
always@(negedge clk)
neg <= d;
assign q = pos & amp;clk | neg & amp;~clk;
endmodule