(Continued from 2.5Finite State Machine(II))
2.5.24 Q3a:FSM [Exams/2014 q3fsm]
Problem description
Consider a finite state machine with inputs s and w. Assume that the FSM starts from a reset state called A, as shown below, the FSM remains in state A as long as s=0, and when s=1, the A state transitions to the B state. Once in state B, the FSM checks the value of w in the next three clock cycles. If w=1 in two of these three clock cycles, the FSM must set the output z to 1 in the next clock cycle. Otherwise, z must be 0. FSM continues to check the next three clock cycles w, and so on. The following timing diagram illustrates the z value output by different w values.
Use as few states as possible, note that the s input is only used in state A, so only w’s input needs to be considered.
Timing example:
Analysis
The conditions for state transition from A to B are very simple. The main thing is to handle the counting of w when switching to state B. Two variables are set here. count is used to count 3 clock cycles. num is used to count the number of w is 1 in 3 clock cycles. The output of z needs to meet the conditions of count=3 and num=2.
Code
module top_module (
input clk,
input reset, // Synchronous reset
inputs,
input w,
output z
);
parameter A=0,B=1;
integer count,num;
reg state,next_state;
\t
always@(posedge clk) begin
if (reset)
state <= A;
else
state <= next_state;
end
\t
always@(*) begin
case(state)
A : next_state = s ? B : A;
B : next_state = B;
endcase
end
\t
always@(posedge clk) begin
if(reset | state==A) begin
count <= 0 ;
num <= 0;
end
else begin
if(count <= 2)
count <= count + 1;
else
count <= 1;
\t\t
if (count == 3)
num <= w;
else
num <= num + w;
end
end
\t
assign z = (num==2) & amp;(count==3);
endmodule
2.5.25 Q3b:FSM [Exams/2014 q3bfsm]
Problem description
Given the state allocation table shown below, implement a finite state machine. Reset should reset the state machine to state 000.
| Present state y[2:0] |
Next state Y[2:0] | < b>Output z | |
| x=0 | x=1 | ||
| 000 | 000 | 000 | 0 |
| 001 | 001 | 100 | 0 |
| 010 | 010 | 001 | 0 |
| 011 | 001 | 010 | 1 |
| 100 | 011 | 100 | 1 |
Code
module top_module (
input clk,
input reset, // Synchronous reset
input x,
output z
);
parameter s0=0,s1=1,s2=2,s3=3,s4=4;
reg [2:0] state,next_state;
\t
always@(posedge clk) begin
if(reset)
state <= s0;
else
state <= next_state;
end
\t
always@(*) begin
case (state)
s0 : next_state = x ? s1 : s0;
s1 : next_state = x ? s4 : s1;
s2 : next_state = x ? s1 : s2;
s3 : next_state = x ? s2 : s1;
s4 : next_state = x ? s4 : s3;
endcase
end
\t
assign z = (state == s3) | (state == s4);
endmodule
2.5.26 Q3c:FSM logic [Exams/2014 q3c]
Problem description
Given the state allocation table as shown below, implement the logical functions Y[0] and z
| Present state y[2:0] |
Next state Y[2:0] | < b>Output z | |
| x=0 | x=1 | ||
| 000 | 000 | 001 | 0 |
| 001 | 001 | 100 | 0 |
| 010 | 010 | 001 | 0 |
| 011 | 001 | 010 | 1 |
| 100 | 011 | 100 | 1 |
Analysis
The understanding of the meaning of the question is as follows: at each clock, the next state of the transition is derived based on y and x, and the next state Y[0] and z are output.
Code
module top_module (
input clk,
input [2:0] y,
input x,
output Y0,
output z
);
parameter s0=0,s1=1,s2=2,s3=3,s4=4;
reg [2:0] next_state;
\t\t
always@(*) begin
case(y)
s0 : next_state = x ? s1 : s0;
s1 : next_state = x ? s4 : s1;
s2 : next_state = x ? s1 : s2;
s3 : next_state = x ? s2 : s1;
s4 : next_state = x ? s4 : s3;
endcase
end
\t
assign Y0 = next_state[0];
assign z = (y == s3) | (y == s4);
endmodule
2.5.27 Q6b:FSM next-state logic [Exams/m2014 q6b]
Problem description
Consider the finite state machine shown below, which has an input w and an output z:
Suppose you wish to use three flip-flops and status codes y[3:1]=000,001,…,101 for states A,B…F. Show the state assignment table for this FSM and derive the next for trigger y[2] The expression of the state.
Show only the next state logic of y[2] (this is more of a finite state machine problem than a programming problem)
State transition table
Draw the following state transition table based on the state transition diagram:
| state y[3:1] |
Next state Y[3:1] | < b>Output z | |
| w=0 | w=1 | ||
| A | B | A | 0 |
| B | C | D | 0 |
| C | E | D | 0 |
| D | F | A | 0 |
| E | E | D | 1 |
| F | C | D | 1 |
Code
module top_module (
input [3:1] y,
input w,
output Y2);
parameter A=0,B=1,C=2,D=3,E=4,F=5;
reg [3:1] next_state;
\t
always@(*) begin
case(y)
A : next_state = w ? A : B;
B : next_state = w ? D : C;
C : next_state = w ? D : E;
D : next_state = w ? A : F;
E : next_state = w ? D : E;
F : next_state = w ? D : C;
endcase
end
\t
assign Y2 = next_state[2];
\t
endmodule
2.5.28 Q6c:FSM one-hot next-state logic [Exams/m2014 q6c]
Problem description
Consider the finite state machine shown below, which has an input w and an output z:
For this question, it is assumed that the state allocation y[6:1] uses a one-hot code, and the encoding method is 000001, 000010,…, 100000 to represent A, B,…, F respectively.
Write the logical expressions for Y2 and Y4 of next-state (assuming one-hot encoding, derive the logistic equation by checking. Testing will be done with non-one-hot inputs to make sure you are not trying to do something more complex)
Code
module top_module (
input [6:1] y,
input w,
output Y2,
output Y4
);
parameter A=6'b000001,B=6'b000010,C=6'b000100,D=6'b001000,E=6'b010000,F=6'b100000;
wire [6:1] next_state;
\t
assign next_state[1] = (y[1] & amp; w) | (y[4] & amp; w);
assign next_state[2] = (y[1] & amp; ~w);
assign next_state[3] = (y[2] & amp; ~w) | (y[6] & amp; ~w);
assign next_state[4] = (y[2] & amp; w) | (y[3] & amp; w) | (y[5] & amp; w) | (y[6] & amp; w);
assign next_state[5] = (y[3] & amp; ~w) | (y[5] & amp; ~w);
assign next_state[6] = (y[4] & amp; ~w);
\t
assign Y2 = next_state[2];
assign Y4 = next_state[4];
\t
endmodule
2.5.29 Q6:FSM [Exams/m2014 q6]
Problem description
Consider the finite state machine shown below, which has an input w and an output z:
Implement this finite state machine.
Code
module top_module (
input clk,
input reset,
input w,
output z);
parameter A=0,B=1,C=2,D=3,E=4,F=5;
reg [3:1] state,next_state;
\t
always@(posedge clk) begin
if(reset)
state <= A;
else
state <= next_state;
end
\t
always@(*) begin
case(state)
A : next_state = w ? A : B;
B : next_state = w ? D : C;
C : next_state = w ? D : E;
D : next_state = w ? A : F;
E : next_state = w ? D : E;
F : next_state = w ? D : C;
endcase
end
\t
assign z = (state == E) | (state == F);
\t
endmodule
2.5.30 Q2a:FSM [Exams/2012 q2fsm]
Problem description
Consider the state diagram shown below
Write complete Verilog code to represent this FSM, using separate always blocks to represent the state table and state triggers. Use continuous assignment statements or always statements to describe the output z of the FSM. Just set the status code how you want to use it.
Code
Just write it directly according to the state transition diagram:
module top_module (
input clk,
input reset, // Synchronous active-high reset
input w,
output z
);
parameter A=0,B=1,C=2,D=3,E=4,F=5;
reg [3:0] state,next_state;
\t
always@(posedge clk) begin
if(reset)
state <= A;
else
state <= next_state;
end
always@(*) begin
case(state)
A : next_state = w ? B : A;
B : next_state = w ? C : D;
C : next_state = w ? E : D;
D : next_state = w ? F : A;
E : next_state = w ? E : D;
F : next_state = w ? C : D;
endcase
end
\t
assign z = (state == E)|(state == F);
\t
endmodule
2.5.31 Q2b:One-hot FSM equations [Exams/2012 q2b]
Problem description
Consider the state diagram shown below
Assume that the one-hot code and status distribution are as follows: y[5:0] = 000001(A), 000010(B), 000100?, 001000(D), 010000(E), 100000(F)
Write logical expressions for signals Y1 and Y3, which are inputs to state flip-flops y[1] and y[3].
Code
module top_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
parameter A=6'b000001,
B=6'b000010,
C=6'b000100,
D=6'b001000,
E=6'b010000,
F=6'b100000;
reg [5:0] state,next_state;
\t
assign next_state[0] = (y[0] & amp; ~w) | (y[3] & amp; ~w);
assign next_state[1] = (y[0] & amp; w);
assign next_state[2] = (y[1] & amp; w) | (y[5] & amp; w);
assign next_state[3] = (y[1] & amp; ~w) | (y[2] & amp; ~w) | (y[4] & amp; ~w) | (y[5] & amp; ~w);
assign next_state[4] = (y[4] & amp; w) | (y[2] & amp; w);
assign next_state[5] = (y[3] & amp; w);
\t
assign Y1 = next_state[1];
assign Y3 = next_state[3];
endmodule
2.5.32 Q2a:FSM [Exams/2013 q2afsm]
Problem description
Consider the FSM described by the state transition diagram shown in the following figure:
This FSM acts as an arbiter circuit that controls access to a certain type of resource by three requesting devices. Each device requests resources by setting the signal r[i]=1, where each r[i] is an input signal to the FSM and represents one of the three devices. As long as there are no requests, the FSM remains in state A. When one or more requests occur, the FSM determines which device receives authorization to use the resource and changes the state of that device with its g[i] signal set to 1. Each g[i] is the output of FSM. There is a priority system where device 1 has higher priority than device 2 and device 3 has the lowest priority. Therefore, if device 3 is the only device making requests when the FSM is in state A, then device 3 will only receive authorization. Once device i is granted authorization by the FSM, it will continue to receive authorization as long as its request r[i]=1. .
Write complete Verilog code to represent this FSM, using separate always blocks to describe the state table and state triggers, and using continuous assignment statements or always blocks to describe the output g[i] of the FSM.
Analysis
The meaning of the question is a bit confusing, but it actually describes this state transition diagram.
Code
module top_module (
input clk,
input resetn, // active-low synchronous reset
input [3:1] r, // request
output [3:1] g // grant
);
parameter A=0,B=1,C=2,D=3;
reg [1:0] state , next_state;
\t
always@(posedge clk) begin
if (!resetn)
state <= A;
else
state <= next_state;
end
\t
always@(*) begin
case (state)
A: begin
if (r == 3'b000) next_state = A;
if (r[1] == 1) next_state = B;
if (r[2:1] == 2'b10) next_state = C;
if (r == 3'b100) next_state = D;
end
B : next_state = (r[1] == 1) ? B : A;
C : next_state = (r[2] == 1) ? C : A;
D : next_state = (r[3] == 1) ? D : A;
endcase
end
\t
assign g[3] = (state == D);
assign g[2] = (state == C);
assign g[1] = (state == B);
\t
endmodule
2.5.33 Q2b:Another FSM [Exams/2013 q2bfsm]
Problem description
Consider a finite state machine that controls a motor of some type. The FSM has inputs x and y from the motor and produces outputs f and g that control the motor. There is also a clock input clk and a low level reset input resetn.
This FSM works as follows. As long as the reset input is set, the FSM stops at the starting position, called state A. When the reset signal is deasserted, the FSM must set the output f to 1 one clock cycle after the next clock edge. The FSM must then monitor the x input. When the value produced in three consecutive clock cycles is 101, the output of g should be set to 1 in the next cycle. When g=1, the FSM monitors the y input. If y has a value of 1 for at most two clock cycles, g will remain high until the reset signal. But if y does not change to 1 within two clock cycles, the FSM should be permanently set to g=0 until the reset signal.
State transition diagram
Code
module top_module (
input clk,
input resetn, // active-low synchronous reset
input x,
input y,
output f,
output g
);
parameter IDLE=0,START=1,A=2,B=3,C=4,D=5,E=6,F=7,G=8;
reg [3:0] state,next_state;
\t
always@(posedge clk) begin
if (!resetn)
state <= IDLE;
else
state <= next_state;
end
\t
always@(*) begin
case(state)
IDLE: next_state = START;
START: next_state = A;
A : next_state = x ? B : A;
B : next_state = x ? B : C;
C : next_state = x ? D : A;
D : next_state = y ? F : E;
E : next_state = y ? F : G;
F : next_state = F;
G : next_state = G;
endcase
end
assign f = (state == START);
assign g = (state == D) | (state == E) | (state == F);
endmodule
This series mainly records my own learning process and simple thinking process, and refers to many other people’s ideas. The questions are all on HDLBits. I organized the description of the questions with the help of a translator and my own understanding. If there are any questions, you are welcome to criticize and correct me.