Tag: vhd

Windows Tip 02: Automatically mount the vhdx (supports bitlocker encryption) virtual disk with one click after booting and unlock bitlocker directly on the command line, automatically escalate the rights and run the bat script&&vhdx virtual disk file compression code as administrator

Take the script code below. It is recommended to use the third or fifth version of the code. Copy it into Notepad. Change the suffix of Notepad to bat file. Put this file in the same directory as the vhdx file and double-click to run it. Why should I use a virtual disk: 1. Used […]

Quickly implement systolic FIR filter based on FPGA, VHDL, systolic array, PE processing unit, FIR filter

Click the blue words to follow us Follow and star the public account, and exciting content will be delivered every day Source: Internet material At present, most methods of implementing FIR (Finite Impulse Response) filters using FPGA (Field Programmable Gate Array) take advantage of the characteristics of the LUT (Lookup Table) in the FPGA and […]

VHDL+FPGA vending machine

Real machine demonstration code show as below library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity vending_machine is port ( clk: in std_logic; reset_in: in std_logic; coin_10_in: in std_logic; coin_5_in: in std_logic; confirm_in: in std_logic; cancel: in std_logic; go: in std_logic; drink_1, drink_2: in std_logic; add_in:in std_logic; less_in:in std_logic; segment_out : out STD_LOGIC_VECTOR (6 down […]

Digital hardware modeling using VHDL, Verilog, SystemVerilog, SystemC, HLS (C++, OpenCL)

Directory introduction 1. Overview of Digital Hardware Modeling 1.1 Hardware Description Language 1.2 System-level modeling language 2. Abstract level hardware model 2.1 Logical Level Model 2.2 Register Transfer Level Model (RTL) 2.3 Transaction Level Model (TLM) 2.4 Behavior/Algorithm Level Model 3. Design and coding practice of hardware model 3.1 Modular design 3.2 Design for reusability […]