1. What is asynchronous FIFO Asynchronous FIFO is one of the FIFO designs (First In First Out, data written first is read out first). Since read and write operations are independent, asynchronous FIFO is often used to transmit multi-bit data across clock domains. Asynchronous FIFO will be referred to as FIFO in the following. Under […]
Tag: verilog
[[FIFO to BRAM IP interconnection, that is, AXIstream is transferred to the verilog code on BRAM]]
FIFO to BRAM IP interconnection, that is, AXIstream is transferred to the verilog code on BRAM control.v module control #( parameter TDATA_WIDTH = 32 , parameter BRAM_A_ADDR_WIDTH = 15 , parameter BRAM_din_WIDTH = 32 , parameter BRAM_B_ADDR_WIDTH = 15 )( input [TDATA_WIDTH – 1 : 0] tdata , input tvaild, input sys_clk, input sys_rst_n , […]
Verilog asynchronous FIFO implementation
module fifo_async#( parameter data_width = 32, parameter data_depth = 8, parameter addr_width = 4 ) ( input rst_n, input wr_clk, input wr_en, input [data_width-1:0] din, input rd_clk, input rd_en, output reg valid, output reg [data_width-1:0] dout, output empty, full output ); reg [addr_width:0] wr_addr_ptr;//Address pointer, one more bit than the address, MSB is used to […]
Verilog implements breathing running water lamp
1. Design purpose Realize a breathing running water lamp that changes from dark to bright within 1 second, and then from bright to dark again in the next 1 second. 2. Design ideas Design a square wave with a gradually increasing duty cycle to change from dark to bright; then the duty cycle gradually becomes […]
Verilog7.2.1 Verilog parallel FIR filter design
FIR (Finite Impulse Response) filter is a finite-length unit impulse response filter, also known as a non-recursive filter. The FIR filter has strict linear phase-frequency characteristics, and its unit response is finite, making it a stable system and widely used in digital communications, image processing and other fields. FIR filter principle FIR filters are finite […]
[[FIFO to multiplier to RAM verilog code and testbnench]]
Verilog code and testbnench for FIFO to multiplier to RAM Only the transmission of a single data is completed. Big data needs to be modified tb or basic connections. FIFO.v //synchronous fifo module FIFO_syn #( parameter WIDTH = 16, // the fifo wide parameter DEPTH = 1024, // depth parameter ADDR_WIDTH = clogb2(DEPTH) // bit […]
[[Verilog code asynchronous FIFO design explanation + source code + tb]]
Design of asynchronous FIFO Use Gray code to determine whether it is really full Used a very clever method Using gray code solves one problem, but it also brings another problem, that is, how to judge empty and full in the Gray code domain. The judgment of “empty” is still based on the fact that […]
CQU digital logic experiment 2 – verilog digital clock source code and constraint files
Some ideas are collected from various materials, and there are also some optimizations. I may modify the code in the future, such as using modular arithmetic for optimization. Hours are LED lights The source files are as follows: `timescale 1ns / 1ps // //Company: // Engineer: // // Create Date: 2023/10/24 10:57:00 // Design Name: […]
verilog FFT Vivado IP core implementation
1. First use matlab to generate 16-bit binary sinusoidal signal data and store it in rom: %Set parameters fi=5000; L=1024; N=16; fs=20000; % generate signal t=0:1/fs:(L-1)/fs; theta=rand()*2*pi; si=sin(2*pi*fi*t + theta); f_s=si/max(abs(si)); Q_s=round(f_s*(2^(N-1)-1)); fid=fopen(‘C:\Users\HLPC\Desktop\Sin.txt’,’w’); for k=1:length(Q_s) B_s=dec2bin(Q_s(k) + (Q_s(k)<0)*2^N,N); for j=1:N if B_s(j)==’1′ tb=1; else tb=0; end fprintf(fid,’%d’,tb); end fprintf(fid,’\r\\ ‘); end fprintf(fid,’;’); fclose(fid); 2. Store […]
Verilog function module – asynchronous FIFO with different read and write bit widths
Table of contents of FIFO series articles: Verilog function module – asynchronous FIFO-CSDN blog Verilog function module – synchronous FIFO-CSDN blog Verilog function module – asynchronous FIFO with different read and write bit widths-CSDN Blog Verilog function module – synchronous FIFO with different read and write bit widths-CSDN Blog Verilog function module – standard FIFO […]