Table of contents of FIFO series articles: Verilog function module – asynchronous FIFO-CSDN blog Verilog function module – synchronous FIFO-CSDN blog Verilog function module – asynchronous FIFO with different read and write bit widths-CSDN Blog Verilog function module – synchronous FIFO with different read and write bit widths-CSDN Blog Verilog function module – standard FIFO […]
Tag: verilog
Macbook M1 uses vscode+iverilog+gtkwave to compile and run Verilog code
Article directory Preface 1. Introduce each tool 2. Install all required tools 1. Installation of Homebrew, a package management tool on MacOS 2.Verilog compiler-iverilog installation 3.ctags installation 4.gtkwave installation 3. Install and configure related plug-ins on vscode 1.CTags Support plug-in 2.Verilog Highlight plug-in 3.Verilog-HDL/SystemVerilog/Bluespec SystemVerilog plug-in 4. Use the built platform to write and simulate […]
Verilog implements decimal frequency division (taking 42.3, 1.5MHZ as an example) and key selection to adjust the frequency from 1 to 10HZ
1. Experiment purpose and requirements Use Verilog programming to implement decimal frequency division. The input clock signal frequency is 50MHz. First, the 42.3MHz clock signal is obtained by decimal frequency division from 50MHz, and then the 42.3MHz clock frequency is divided to obtain 1Hz, 2Hz, 3Hz, 4Hz, 5Hz, 6Hz, and 7Hz. , 8Hz, 9Hz, 10Hz […]
Verilog keyword [FPGA]
Grammar URL: 1.1 Verilog Tutorial | Newbie Tutorial Official video: 04-Lecture 4-First introduction to Verilog_bilibili_bilibili Pin status: Pin status: 0 (0 or false), 1 (1 or true), x/X (unknown), z/Z (high impedance) Input input wire // is a bool type, used to bind FPGA pins input wire[7:0] //It is byte type Output output wire // […]
Verilog function module – synchronous FIFO
Table of contents of FIFO series articles: Verilog function module – asynchronous FIFO-CSDN blog Verilog function module – synchronous FIFO-CSDN blog Verilog function module – asynchronous FIFO with different read and write bit widths-CSDN Blog Verilog function module – synchronous FIFO with different read and write bit widths-CSDN Blog Verilog function module – standard FIFO […]
Verilog function module – asynchronous FIFO
Table of contents of FIFO series articles: Verilog function module – asynchronous FIFO-CSDN blog Verilog function module – synchronous FIFO-CSDN blog Verilog function module – asynchronous FIFO with different read and write bit widths-CSDN Blog Verilog function module – synchronous FIFO with different read and write bit widths-CSDN Blog Verilog function module – standard FIFO […]
verilogFinite state machine
1. What is a finite state machine Finite State Machine (Finite State Machine, abbreviated as FSM) is used to describe a sequential circuit that converts between a limited number of states according to certain rules. The structure of the circuit described by the finite state machine is clear, especially for circuits with more complex functions, […]
Multiplier implemented based on Wallace tree + booth2-bit encoding + 32 compressor (Verilog implementation)
Write a custom directory title here Multiplier based on booth2-bit encoding + 32 compressor + Wallace tree implementation (Verilog implementation) Principle part booth2 bit encoding 32 compressor wallace tree Code Wallace 32compressor Testbench References Multiplier implemented based on booth2-bit encoding + 32 compressor + Wallace tree (Verilog implementation) Principle part The principle part is only […]
Verilog implementation of CRC (cyclic redundancy check)
Algorithm introduction: A channel coding technology used to detect errors that may occur after data transmission or storage. It uses modulo 2 division for verification. It has fast calculation speed and strong error detection capabilities. It has different standard parameter models. The higher the standard, the higher the error detection. The better the capability and […]
mVerilog implementation of GFDM modulation and demodulation system based on FPGA, including testbench simulation test files
Table of Contents 1. Algorithm simulation effect 2. Summary of theoretical knowledge involved in algorithms 2.1 Subcarrier modulation 2.2 Pulse shaping filtering 2.3 GFDM signal generation 3.Verilog core program 4. Complete algorithm code file 1. Algorithm simulation effect This system was developed on the Vivado2019.2 platform, and the test results are as follows: GFDM modulated […]