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When doing logic synthesis and placement and routing for FPGA, timing constraints need to be set in the tool. Usually, in FPGA design tools, FPGA contains four paths: pure combinational logic from input port to register, from register to register, from register to output, and from input to output.
Usually, these types of paths need to be constrained separately so that the design tool can obtain optimal results. These paths are discussed separately below.
(1) From input port to register:
This path constraint is to allow the FPGA design tool to optimize the path delay from the input port to the first-level register as much as possible, so that it can ensure that the system clock reliably collects the signal from the external chip to the FPGA. Constraint name: input delay. The influence of constraints mainly has four factors: Tco of the external chip, signal delay Tpd on the circuit board, Tsu of FPGA, and clock delay Tclk. The parameters of Tco usually need to be checked in the data sheet of the external chip. Calculation formula: input delay = Tco + Tpd + Tsu-Tclk. For Tsu of FPGA, you also need to check the manual of the FPGA chip. Different FPGA speed levels have different parameters. Tpd and Tclk need to be calculated based on the actual parameters of the circuit board. Usually, every 10cm line length can be calculated as 1ns. For example: the system clock is 100MHz, the maximum delay on the circuit board is 2ns, the maximum clock delay is 1.7ns, Tco is 3ns, and the Tsu of the FPGA is 0.2ns. Then the value of the input delay: max Input delay = 2 + 3 + 0.2-1.7=3.5ns. The meaning of this parameter is to allow the FPGA design tool to control the path delay (including gate delay and line delay) between the FPGA input port and the first-level register to 10ns -3.5ns=within 6.5ns.
(2) Register to register:
This path constraint is to allow the FPGA design tool to optimize the path from register to register in the FPGA, so that the delay time must be less than the clock cycle, so as to ensure that the signal is transmitted reliably. Since this path only exists inside the FPGA, it can usually be constrained by setting the clock frequency. For a more in-depth optimization method, you can also add appropriate constraints to the input of the register and the output of the register to enable the logic synthesizer and router to specifically optimize a certain path. You can also set the maximum number of fan-outs to force the tool to logically copy it, reducing the number of fan-outs and improving performance.
(3) Register to output:
This path constraint is to allow the FPGA design tool to optimize the path from the last-level register to the output port within the FPGA to ensure that its output signal can be correctly picked up by the next-level chip. The name of the constraint: output delay. The influence of the constraint conditions mainly has three factors: Tsu of the external chip, signal delay Tpd on the circuit board, and clock delay Tclk. The parameters of Tsu usually need to be checked in the data manual of the external chip. Calculation formula: output delay = Tsu + Tpd-Tclk. For example: system clock 100MHz, maximum delay on the circuit board 2ns, maximum clock delay 1.7ns, Tsu 1ns, output delay value: max output delay = 1 + 2-1.7=1.3 ns. The meaning of this parameter is to allow the FPGA design tool to control the path delay (including gate delay and line delay) between the last stage register and the output port within 10ns-1.3ns=8.7ns.
(4) From input port to output port:
This path refers to the delay of combinational logic, which means that the signal does not pass through any registers from input to output. To add constraints to this kind of path, you need to virtualize a clock, and then use constraints to specify which paths are subject to the constraints of the virtual clock. There are corresponding constraints in Synplifypro and Precision to handle this kind of path.
Regarding some parameters of input and output delay, it is not easy to combine these parameters with xilinx software. In the past, it seemed that no one paid much attention to the setting of constraints. Most of the time, they would put it on the board first and then adjust it through signaltap and Chipscope. When the scale of FPGA increases, wiring once takes a long time, and the disadvantages of this method become more and more serious. In fact, we can learn from the ASIC design method: add relatively complete constraints, and then solve the problem through RTL simulation, timing analysis, and post-simulation, and try to avoid debugging on the FPGA circuit board. altera was the first to realize this and adopted Synopsys’ SDC format. The SDC format is also supported by logic synthesizers. And the setting method is relatively easy to master. This post will discuss the constraint setting method of this format in detail.
Clock setting method: The clock should be divided into two types, one is the clock input directly from the port, and the other is the clock generated inside the FPGA. The internally generated clock is divided into two types, one coming from the phase-locked loop (including altera’s PLL and Xilinx’s DLL) and one coming from the logic unit. This is the case for general counter frequency division, for example. The clock from the phase-locked loop can be added directly through the port, because general synthesis tools and wiring tools can automatically transfer the clock constraints of the port to the phase-locked loop, and automatically apply them to the next phase according to the frequency multiplication relationship of the phase-locked loop. class. What comes out of the logical unit needs to be constrained separately.
In the SDC format, the command to create a clock, create_clock, must be followed by three parameters: name, period, and waveform. The meaning of name refers to the name of the clock constraint created, not the name of the clock itself. To associate this constraint with the clock signal, something needs to be added later. The default unit of period is ns. Waveform is used to specify the duty cycle. In addition to these three parameters, the get_ports command is often added to specify the clock input port. The following example is a more complete example of setting the clock:
create_clock -name clk1 -period 10.000 –waveform { 2.000 8.000 } [get_ports sysclk]
This example shows that there is a constraint on clk1, in which the clock period is set to 10ns, the duty cycle is 2ns low level, and 8ns high level. This constraint called clk1 is for the sysclk port.
If the internal phase-locked loop is used to divide the frequency of many other clock constraints, there is no need to impose other constraints. The logic synthesizer and router can automatically calculate based on the parameters of the phase-locked loop. If the signal is divided by the internal logic unit, you must use get_registers to specify the register name of the frequency division. For example, the above example:
create_clock -name clk1 -period 10.000 –waveform { 2.000 8.000 } [get_registers cnt_clk].
For the divided clock signal of the logic unit, you can also use the command create_generated_clock, which will be more accurate. Examples are as follows:
create_generated_clk -name clk2 -source [getports sysclk] -div 4 [get_registers cnt_clk]
This constraint command describes a clk2 constraint. The constraint object is the clock obtained by dividing sysclk by 4 times. This clock is generated by the cnt_clk register.
In high-speed systems, the description of the clock may require more and more detailed descriptions. For example, you will be asked to describe clock jitter and clock delay. In the SDC file format, it can be described by two commands: set_clock_uncertainty and set_clock_latency.
Clock delay is relatively simple. Delay is generally divided into external delay and internal clock line network delay. Usually, only the external delay is constrained when constraining. Just add the -source parameter after the set_clock_latency command. For example:
set_clock_latency -source 2 [get_clocks {clk_in}]
Clock jitter is a little more complicated. Because this value will not only affect the analysis of Tsu, but also the analysis of Thold. Therefore, there are more parameters to use set_clock_uncertainty. If you want to understand the impact of this command on system timing analysis, you need to explain more about the concept of altera’s delay calculation.
For the case of set_clock_uncertainty, it is slightly more complicated. Because the value of set_clock_uncertainty affects both the calculation of the setup time and the calculation of the hold time, it needs to be specified separately when setting:
set_clock_undertainty –setup 0.500 –from clkA –to clkA
set_clock_uncertainty –hold 0.300 –from clkA –to clkA
The previous content provides calculation methods for calculating input and output delays. The output delay command is set_output_delay. There are several parameters to add: reference clock, maximum and minimum values, and port name. As described in the example below.
set_output_delay -clock CLK -max 1.200 [get_ports OUT]
set_output_delay -clock CLK -min 0.800 [get_ports OUT]
The command for input delay is very similar:
set_input_delay -clock CLK -max 2.000 [get_ports IN]
set_input_delay -clock CLK -min 1.600 [get_ports IN]
For some special design requirements, such as unconcerned data transfer paths and multi-shot paths, it is also necessary to add false path and Multicycle settings. These two constraints are relatively simple and easy to set, but they are very critical. If the setting is not good, system performance will be greatly reduced. false path refers to a path whose delay calculation is not considered in timing analysis. For example, there are some circuits that span clock domains. Setting method:
set_false_path -from [get_clocks clkA] -to [get_clocks clkB]
set_false_path -from regA -to regB
The first command sets all paths from clock domain clkA to clock domain clkB to false paths. The second command sets the path from regA to regB to false path. Both paths will be ignored when doing timing analysis. The setting method of multicycle is similar to the setting method of false path.
In order for the logic synthesizer and placement and router to find the path that really needs to be optimized based on timing constraints, we also need to analyze the timing report. Combined with the timing report of the logic synthesizer and the timing report of the router, through analysis, you can see to find out whether the potential of the chip has been fully exploited
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