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In the field of electronic design, multi-channel broadband signals usually need to be collected, processed and transmitted in real time. Traditional signal acquisition and transmission systems use special integrated circuits to control peripheral circuits such as A/D converters. Due to the shortcomings of ASICs such as low clock frequency, poor flexibility, low real-time performance, slow transmission speed, and poor versatility, it is difficult to meet the requirements for high-speed broadband signal acquisition and processing. FPGA has the characteristics of high clock frequency, fast speed, high real-time acquisition, and flexible control. It is more suitable for high-speed digital signal processing when combined with peripheral circuits such as A/D converters. Compared with electrical transmission, optical fiber transmission has the characteristics of wide transmission frequency, large communication capacity, low transmission loss, strong anti-electromagnetic interference performance, strong radiation resistance, good confidentiality, light weight, etc., and is widely used in the communication field.
This paper proposes a high-speed digital signal transmission scheme based on FPGA and optical fiber transmission. A high-performance FPGA with a transceiver is used as the control core to control the peripheral A/D converter and data processing, and transmit data through optical fiber media to meet the requirements of real-time processing and transmission of high-speed digital signals.
Part11 Overall System Design Plan
The optical fiber transmission system is a transmission system that uses light waves as the information carrier, optical fiber as the transmission medium, and uses light to transmit information. The overall block diagram of the optical fiber transmission system is shown in Figure 1. The sending end is mainly composed of A/D acquisition, FPGA data preprocessing, and optical fiber sending modules; the receiving end is mainly composed of optical fiber receiving modules, FPGA data post-processing, and D/A conversion modules. The two communicate via fiber optics. 
At the sending end, the external input analog signal is first preprocessed, and then converted into a digital signal through the A/D converter and sent to the FPGA for processing. According to the requirements of data transmission and communication protocols, FPGA encodes and frames the preprocessed A/D data. Then the IP core inside the FPGA performs parallel-to-serial conversion, and finally the optical transceiver module completes the electro-optical conversion and then sends it out through the optical fiber.
At the receiving end, the optical transceiver module converts the received optical signal into an electrical signal to complete the conversion of high-speed serial data to parallel data; then, the converted parallel data is sent to FPG A, and the FPGA completes the deframing and deframing of the signal. Decoding and post-processing, this process is the reverse process of the sending end. Finally, the received data is restored to analog signals through the D/A converter.
Part22 Hardware Circuit Design
2.1 Transmitter hardware circuit design
The programmable logic device FPGA is the main control chip and the core of the system. The design uses Altera’s Arria GX series chip EP1AGX50CF48416 with transceiver. The chip integrates 4 transceiver channels, with transmission data rates ranging from 600 Mbit·s-1 to 3.152Gbit·s-1. Each transceiver channel consumes only 125 mW power at 2.5 Gbit·s-1; The transceiver can equalize the serial channel using fixed equalization settings for transmit pre-emphasis and receive equalization; the transceiver supports serial loopback, reverse serial loopback, and a pseudo-random binary sequence (PRBS) generator and checker. The dedicated transceiver interface circuit is shown in Figure 2. RREFB14 is connected to a 2kΩ/1% reference resistor, and other unused transceiver pins are connected to the power supply or ground through 10kΩ resistors.
The optical transceiver module uses the MXP-243S-X optical transceiver, which can process a data rate of 1.25 Gbit·s-1, a single power supply of 3.3 V, differential LVPECL level input and output, transmitting and receiving parts Independent. The differential input impedance of the transmitting part is 100 Ω, and the wavelength of the transmitted optical signal is 1310nm. The circuit diagram of the optical transmitter is shown in Figure 3. The transmitted differential data is connected to the transmitting pins G4 and G5 of the FPGA’s dedicated transceiver. The control pin is directly connected to the ordinary L/O pin and connected to the power supply through a pull-up resistor.
2.2 Receiver circuit design The receiver FPGA also uses Altera’s Arria GX series chip EP1AGX20CF48416. The optical transceiver module still uses the MXP-243S-X optical transceiver. For circuit connection, you only need to directly connect the RD + and RD- ports in Figure 3 to the optical transceiver TLK1501. In order to match the lower-level system, TI’s TLK1501 is selected as the serial transceiver designed to support a data bandwidth of up to 1.2 Gbit·s-1. It integrates 8 B/10 B encoder, parallel-to-serial converter, differential input and output interface, 8 B/10 B decoder, serial-to-parallel converter, clock management module, etc. There is an internal self-test loop for easy self-test, integrated signal loss detection, and support for hot plugging. The circuit is shown in Figure 4.
R201, R202, R204, and R205 are 50Ω matching resistors, R203 is a reference resistor 200Ω, and R206 and R207 provide the bias voltage required for terminal matching.
Part33 Software Design
The design adopts a top-down modular design method and uses Verilog hardware language programming to realize FPGA control of peripheral circuits such as chips at the optical fiber interface, A/D and D/A converters.
3.1 Sender-side FPGA programming
The transmitter FPGA logic design mainly includes sampling storage logic, verification, framing and encoding logic and optical transmitter interface logic.
3.1.1 Sampling storage logic
The sampling storage logic completes data collection and real-time storage. Its logical form and principle block diagram are shown in Figure 5.
AT84AS001 is an ADC chip. The input differential data is directly connected to the dedicated differential pins of the FPGA. The acquisition and storage control logic includes LVDS reception and data reorganization modules. The LVDS receiver changes the double-edge clock into a single edge. The data reorganization module reorders the data and restores the original data flow. Finally cached in FIFO.
3.1.2 Verification, framing and encoding logic
The verification, framing and encoding logic completes the data format conversion, and performs CRC encoding, framing, 8B/10B encoding and parallel-to-serial conversion on the processed data. The algorithm flow is shown in Figure 6.
3.1.3 Optical transmitter interface logic
The optical transmitter interface logic completes the conversion of frame data into high-speed serial data streams. Directly utilize the dedicated transceiver inside the FPGA, and its structure is shown in Figure 7.
The frame data is first transmitted to the south through the phase compensation FIFO module for phase compensation to offset the clock phase difference, and then the data is converted into 8 bits through a byte serializer, and then 8B/10B encoding is performed, and converted into a high-speed data stream by the serializer. Outputted by a dedicated differential output port.
3.2 Receiver FPGA programming
The transmitter FPGA logic design mainly includes optical receiver interface logic and decoding, deframing and verification logic.
3.2.1 Optical receiver interface logic
TLK1501 has a state machine that is responsible for monitoring different working states, namely synchronization capture mode, synchronization mode and error detection mode. After power-on or reset, the state machine enters the synchronization capture mode. When it receives three consecutive IDLE codes or carrier extension codes or one valid data or error delay, it enters the synchronization mode. Perform normal reception and transmission of data in synchronous mode. In this mode, the TLK1501 receives an invalid code and the state machine immediately enters error detection mode. When detection mode receives 4 consecutive invalid codes, TLK1501 immediately re-enters capture mode. The TLK1501 synchronization state machine is shown in Figure 8.
The optical receiver interface logic completes the conversion of high-speed serial data streams to low-speed parallel data. The serial transceiver TLK1501 is used, and its structural block diagram is shown in Figure 9.
The high-speed data input from the dedicated differential port undergoes clock recovery through the clock recovery unit, undergoes 10B/8B decoding after serial-to-parallel conversion, and is finally transmitted to the FPGA for deframing operation.
3.2.2 Decoding, deframing and verification logic
The decoding, deframing and verification logic completes the data format conversion, and performs 10B/8B decoding, deframing and CRC verification on the received data to obtain valid data. The algorithm flow is shown in Figure 10.
Part44 Experimental Simulation and Waveform
Figure 11 shows the effect of TLK1501 stably transmitting data. As can be seen from the figure, TLK1501 achieves real-time and stable data transmission. 
Figure 12 is the simulation waveform diagram of the data transmission and reception error test. data_all is the total amount of data that has been tested up to the current clock, and data_err is the total amount of data with transmission errors up to the current clock. It can be seen that after tens of billions of data are transmitted, the bit error is still zero. 
Part55 Conclusion
Researched and designed a high-speed digital signal transmission scheme based on FPGA and optical fiber communication. Experimental results show that this solution achieves real-time transmission of high-speed digital signals and has the advantages of low signal transmission error rate, stable system performance, and strong anti-interference. Due to actual needs, the system uses TLK1501 at the receiving end, which limits The transmission rate of optical fiber can be further improved if the optical fiber transceiver module inside the FPGA is used.
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