Looking at the life of interruption from the perspective of software and hardware interaction

For example, there are four interrupt sources A, B, C, and D, and their priorities are arranged in descending order from A->B->C->D. While the CPU is executing the main program, interrupt requests from B and C appear at the same time. Since B has a higher level than C, B’s service program is executed first.

When B’s service program is executed and returns to the main program, since C’s request has not been canceled, the CPU executes C’s interrupt service program again. If there is another request from D at this time, the CPU will not respond because the level of D is lower than C. When C’s service program is executed and returns to the main program, D’s service program is executed again.

If an A request occurs again at this time, because the A level is higher than D, the CPU suspends the execution of the D level interrupt service program and switches to execute the A level interrupt service routine. After the A level service routine is completed, it then executes D. level interrupt service routine. The above interrupt processing diagram is as follows:

2. Shielding technology

• 1) Mask flip-flop and mask word: In the program interrupt interface circuit, there are completion trigger D, interrupt request flip-flop INTR and mask flip-flop MASK.

In the program interrupt interface circuit, there are three important components: Complete flip-flop D, Interrupt request flip-flop INTR and Mask flip-flop MASK . These components all play their own roles to implement program interrupt handling functions.

Completion trigger D: When the device work is completed, D will be set to 1, which means that the interrupt source is ready to send an interrupt request to the CPU.

Interrupt request trigger INTR: When the device issues an interrupt request, INTR will be set to 1. This trigger is used to send an interrupt request to the CPU.

Mask flip-flop MASK: Each interrupt source has a corresponding mask flip-flop. If the interrupt source is masked (that is, MASK=1), then even if INTR is set to 1, the CPU will not respond to the interrupt request. In other words, masking triggers prevents specific interrupt sources from sending interrupt requests to the CPU.

All mask flip-flops combined together form a mask register.

For example, the priority levels of the four interrupt sources A, B, C, and D are arranged in descending order A->B->C->D. According to this order, the trajectory of the CPU execution program is as shown in the figure below. When 4 interrupt sources are raised at the same time

Without changing the order in which the CPU responds to interrupts, the order in which the CPU processes interrupts can be changed by changing the mask word. For example, changing the mask words of the above four interrupt sources changes their processing order to:

When the CPU is running the program, if four interrupt sources A, B, C, and D make requests at the same time, the CPU will first respond to and process the request from interrupt source A according to the level of the interrupt. Since the mask word of A is 1111, the mask All interrupt sources are eliminated, so program A can be completely executed and then return to the main program.

Since the interrupt requests of B, C, and D have not yet been responded to, and B’s response priority is higher than the others, the CPU responds to B’s request and enters B’s interrupt service routine.

In B’s service program, since a new mask word 0100 is set, that is, A, C, and D can interrupt B, and A program has been executed, C’s response priority is higher than D, so the CPU responds to C and enters C. service program.

In C’s service program, since the mask word 0110 is set, A and D can interrupt C. A has been executed, so the CPU responds to D and executes D’s interrupt service program.

After D is finished, return to program C. After program C is executed, return to program B.

After program B is completed, return to the main program.

During the interrupt processing process, the CPU will first check INTR. If INTR is 1, then the CPU will further check the corresponding mask flip-flop (MASK). If MASK is also 1, then the interrupt request of the interrupt source will be masked, and the CPU will not Will respond; if MASK is 0, then the CPU will respond to this interrupt request and execute the corresponding interrupt service routine.

This process is automatic and does not require programmers to explicitly write relevant instructions. In hardware design, programmers need to set the values of INTR, D and MASK according to actual needs to achieve correct interrupt processing.

Are you a software programmer or a hardware programmer?

3. The significance of shielding technology

Shielding technology also brings greater flexibility to program control. For example, in floating-point operations, when the programmer estimates that “order overflow” may occur when executing a certain program, but does not want the machine to stop due to “order overflow”, a shield can be set for this purpose. word, so that the mask bit corresponding to “stage overflow” is “1”In this way, even if a “stage overflow” occurs, the machine will not stop.

In some cases,programmers may wish to disable other interrupts before performing certain operations to prevent these interrupts from interfering with ongoing operations. By setting the corresponding interrupt mask flip-flop to 1 (that is, masking the interrupt), the programmer can ensure that during these operations, there will be no interference from interrupt requests from that interrupt source.

In addition, blocking technology can also be used to implement priority control. For example, if there are multiple interrupt sources in the system, and the programmer wants not to respond to other low-priority interrupts before certain operations are completed, the CPU’s processing priority for different interrupt sources can be changed by adjusting the mask word settings** class**. In this way, programmers can better control the execution flow of the program and the order of interrupt processing, thereby optimizing the performance and response speed of the system.

In addition,masking technology can also be used to debug programs. When there are certain unforeseen errorsin the program, programmers can disable certain interrupt requests by setting corresponding mask words to avoid these errors from interfering with program execution. At the same time, by viewing the blocked interrupt service routine table, programmers can discover errors in time and take appropriate measures to repair them.

Masking technology provides programmers with a powerful tool to more flexibly control program execution and interrupt handling. Through reasonable use of shielding technology, the stability and performance of the system can be improved to meet various complex application requirements.

An interrupted life

How to view an interrupt from the perspective of software and hardware? What should the complete process of an interrupt look like?

• Create the corresponding interrupt service function** (software):
  When writing an operating system or application program, it is necessary to create a corresponding interrupt service function (Interrupt Service Routine, ISR) for each interrupt source. This function is a program used tohandle specific interrupts**. When an interrupt occurs, the processor will jump to this function to perform the corresponding operation.

• Bind the interrupt service function to a specific interrupt number, also called interrupt registration** (software)**:
  In the operating system or hardware system, each interrupt source needs to be bound to the corresponding interrupt number. This process is usually completed during initialization to ensure that the corresponding interrupt service function can be called correctly when an interrupt occurs. This binding can be implemented programmatically. For example, in Linux systems, the register_interrupt function can be used to register the interrupt service function to a specific interrupt number.

• Module generates raw interrupt (logical):
  When a hardware device requires interrupt processor service, it sends an interrupt request to the interrupt controller. This request may be sent by a hardware signal line or by a specific protocol (such as PCI Express). For example, when a hard disk read or write error occurs, the hard disk controller will send an interrupt request to the interrupt controller.

A raw interrupt means that when a device or component requires the CPU’s attention, it requests the CPU’s attention by sending an interrupt signal to the CPU. This interrupt signal is generated by a hardware circuit and is an electrical signal that can be sensed by the CPU. Raw interrupts are usually spontaneously generated by hardware devices or systems, such as keyboard keys, timers, printers, etc.

• After int_mask judgment, it is not masked and the interrupt status is raised (logical):
  After the interrupt controller receives the interrupt request, it will determine whether the interrupt is masked based on int_mask. If it is not masked, the interrupt status is pulled high so that the processor can sense the interrupt request. In this process, the interrupt controller will determine whether the current interrupt is masked based on the bitmap in int_mask. If it is not masked, the corresponding interrupt status bit will be pulled high.

The int_mask of the interrupt is the interrupt mask. It is a read-only register that shows which bits are currently masked and which bits are not masked/enabled. By setting int_mask, certain interrupts can be masked or enabled.

• After the top-level signal xxx_int of the module is pulled high, it is sent to the corresponding bit (logic) of the processor (CPU & MCU, etc.) corresponding to the specific interrupt number:
  When the interrupt status is pulled high, the module’s top-level signal xxx_int will be pulled high, and this signal is sent to the corresponding bit of the processor corresponding to the specific interrupt number. This process is implemented by hardware logic and is usually related to the architecture of the processor and the design of the interrupt controller. For example, in an x86 architecture computer, when an interrupt status is pulled high, the corresponding processor will send the corresponding interrupt signal to the processor through the APIC bus.

• After the interrupt signal is pulled high, enter the interrupt service function **(logic)** of the corresponding bit:
  When the corresponding bit of the processor receives an interrupt signal, the processor will jump to the corresponding interrupt service function to handle the interrupt. This process is done automatically by the hardware and is usually related to the architecture of the processor and the design of the operating system. For example, in an x86 architecture computer, when the processor receives an interrupt signal, it will jump to the corresponding interrupt service function through the CSIP and IVT registers to perform the corresponding operation.

At the hardware level, the interrupt system requires hardware devices (such as interrupt controllers) to capture interrupt signals and pass the signals to the CPU. After receiving the interrupt signal, the CPU will search the corresponding entry address in the interrupt vector table according to the interrupt number, and then jump to this address to execute the corresponding interrupt service routine. This process is automatically performed by hardware and does not require the participation of software.

• Contents of executing the interrupt service function (software):
  In the interrupt service function, corresponding operations will be performed according to the needs of the device, such as reading data, sending responses, etc. This process is implemented by software and is usually related to the design of the device’s driver and operating system. For example, in a Linux system, after executing an interrupt service function, it usually handles device events by calling the handle_irq_event function.

MORE

Interrupt vector table

In the ARM processor, when an interrupt signal is triggered, the interrupt controller will issue an interrupt request and pass the request to the CPU.

After the CPU receives the interrupt request, it will search the corresponding interrupt service program entry address in the interrupt vector table according to the interrupt number.

The interrupt vector table is a predefined table in which each entry contains an entry address to a specific interrupt service routine.

When the CPU receives an interrupt request, it will search for the corresponding entry in the table based on the interrupt number, obtain the corresponding entry address, and jump to the address to execute the corresponding interrupt service routine.

In this process, programmers can define the entry addresses of interrupt service routines for different interrupt sources by setting entries in the interrupt vector table.

This allows you to implement custom interrupt processing logic and perform corresponding operations based on different interrupt events.

It should be noted that in ARM processors, different working modes (such as User, FIQ, IRQ, SVC, etc.) use different register sets and privilege levels.

When an interrupt occurs, the CPU determines the entry address of the interrupt service program to jump to based on the current working mode and the entries in the interrupt vector table.

Then it saves the CPU state to the corresponding stack and jumps to that address to execute the interrupt service routine.

In ARM processors, the interrupt vector table is a predefined table, which is usually defined and initialized by the boot loader (Bootloader) or the operating system when the system starts.

The boot loader is responsible for loading and starting the operating system's kernel when the system boots. During this process, it reads the interrupt vector table data in memory and copies it to the specified memory address.

This address is usually determined during system configuration to ensure that the interrupt vector table can be accessed by the CPU at the correct location.

The operating system also takes over the management and configuration of the interrupt vector table after startup. It maps the entries in the interrupt vector table to the corresponding interrupt service program entry address based on the configuration of the system interrupt controller and other hardware devices.

In this way, when an interrupt occurs, the CPU can find the corresponding entry in the interrupt vector table according to the interrupt number, and jump to the corresponding address to execute the corresponding interrupt service routine.

It should be noted that the definition and specific implementation of the interrupt vector table may vary depending on different ARM processor architectures and system designs.

Therefore, where and how it is defined may vary depending on the hardware platform and operating system.

This part also involves compilation and memory distribution, so I won’t go into details here. Let’s take a look at it when you have the opportunity.

Raw Interrupt and Masked Interrupt

Raw Interrupt and Masked Interrupt are two types of interrupts, which are used to handle interrupts in ARM processors.

Raw Interrupt refers to the status of the external interrupt source. Regardless of whether the ARM chip blocks the interrupt source, the interrupt status of this interrupt source will be stored in the register and can be read through the corresponding function.

Masked Interrupt refers to whether it is masked or not. In the ARM processor, each interrupt source has a corresponding mask flip-flop. If the interrupt source is masked (that is, MASK=1), then even if INTR is set to 1, the CPU will not respond to the interrupt request. . In other words, masking triggers prevents specific interrupt sources from sending interrupt requests to the CPU. All mask flip-flops are combined to form a mask register.

Reference materials

I hope you gain something from reading it. If there are any bugs in the content, please correct me.

Thanks to the senior brothers for sharing their excellent books and blogs.

• Embedded basics-interrupt handling process
• interrupt masking technology
• “Linux Manual”
• “In-depth Linux Device Driver Kernel Mechanism”
• “Run Linux Kernel”
• interrupt masking technology