This is a function for programming the timing of the nor memory. The function form is void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct). There is only one parameter in it. This parameter is a pointer type and points to a data structure. This data structure holds the configuration of the timing. Each parameter of , the details of this structure are:
1 typedef struct
2 {
3 uint32_t FSMC_Bank;//nor is divided into four blocks, where this parameter indicates which block is programmed
4 uint32_t FSMC_DataAddressMux;//Whether address\data is multiplexed
5 uint32_t FSMC_MemoryType;//Memory type
6 uint32_t FSMC_MemoryDataWidth; //Data bus width 8 bits/16 bits
7 uint32_t FSMC_BurstAccessMode;//Whether to perform group mode access
8 uint32_t FSMC_WaitSignalPolarity;//Waiting for signal validity level
9 uint32_t FSMC_WrapMode;//This bit determines whether the controller supports splitting unaligned AHB group operations into 2 linear operations; this bit is only valid in the group mode of the memory.
10 uint32_t FSMC_WaitSignalActive; //When the flash memory is in burst transfer mode, the NWAIT signal indicates whether the data coming out of the flash memory is valid or whether a wait cycle needs to be inserted. This bit determines whether the memory generates the NWAIT signal one clock cycle before the wait state, or generates the NWAIT signal during the wait state.
11 uint32_t FSMC_WriteOperation; //This bit indicates whether FSMC allows/disables write operations to the memory.
12 uint32_t FSMC_WaitSignal; //When the flash memory is in burst transfer mode, this bit allows/disables the insertion of wait states through the NWAIT signal.
13 uint32_t FSMC_ExtendedMode;//This bit allows FSMC to use the FSMC_BWTR register, which allows different timings for reading and writing.
14 uint32_t FSMC_WriteBurst; //For flash memory in burst transfer mode, this bit allows/disables the insertion of wait states through the NWAIT signal. The synchronous burst transfer protocol enable bit for read operations is the BURSTEN bit of the FSMC_BCRx register.
15 FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; //Read timing configuration pointer
16 FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;//Write timing configuration pointer
17 }FSMC_NORSRAMInitTypeDef;
The structure of the two pointers is as follows
1 typedef struct
2 {
3 uint32_t FSMC_AddressSetupTime; //These bits define the setup time of the address and are suitable for NOR flash operations in SRAM, ROM and asynchronous bus multiplexing modes.
4 uint32_t FSMC_AddressHoldTime; //These bits define the hold time of the address, suitable for NOR flash operation in SRAM, ROM and asynchronous bus multiplexing mode.
5 uint32_t FSMC_DataSetupTime; //These bits define the retention time of data, suitable for NOR flash operations in SRAM, ROM and asynchronous bus multiplexing mode.
6 uint32_t FSMC_BusTurnAroundDuration;//These bits are used to define the delay on the bus after a read operation (only applicable to NOR flash memory operations in bus multiplexing mode). After a read operation, the controller needs to send out data on the data bus for the next operation. Address, this delay is to prevent bus conflicts. If the extended memory system does not include memories in bus multiplexing mode, or the slowest memory can return the data bus to a high-impedance state within 6 HCLK clock cycles, this parameter can be set to its minimum value.
7 uint32_t FSMC_CLKDivision;//Define the period of the CLK clock output signal, expressed in the number of HCLK cycles:
8 uint32_t FSMC_DataLatency; //NOR flash memory in synchronous group mode needs to define the number of memory cycles to wait before reading the first data. This time parameter is not expressed in HCLK, but in flash clock (CLK). This parameter has no effect when accessing asynchronous NOR flash, SRAM or ROM. When operating CRAM, this parameter must be 0.
9 uint32_t FSMC_AccessMode; //Access mode
10 }FSMC_NORSRAMTimingInitTypeDef;
The function content is as follows
1 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
2 {
3 /* Verify parameters*/
4 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
5 assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
6 assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
7 assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
8 assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
9 assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
10 assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
11 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
12 assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
13 assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
14 assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
15 assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
16 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
17 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
18 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
19 assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
20 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
21 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
22 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
23 /* Combine the control parameters into 32-bit data and send it to the FSMC_Bank register, where FSMC_Bank is the offset address*/
24 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
25 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
26 FSMC_NORSRAMInitStruct->FSMC_MemoryType |
27 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
28 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
29 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
30 FSMC_NORSRAMInitStruct->FSMC_WrapMode |
31 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
32 FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
33 FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
34 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
35 FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
36 //If it is NOR memory
37 if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
38 {
39 //Allow access operations to NOR flash memory
40 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
41 }
42 /* Combine the parameters and operate the timing configuration register FSMC_Bank as the offset address + 1 ( + 4) points to the timing configuration register */
43 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank + 1] =
44 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
45 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
46 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
47 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
48 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
49 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
50 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
51 /* Whether to use write timing*/
52 if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
53 {
54 //Whether the write timing configuration parameters are correct
55 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
56 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
57 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
58 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
59 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
60 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
61 //If correct, the combined parameters are assigned to the write timing configuration register. FSMC_Bank is the offset address as above, and the base address is the base address of the write timing configuration register group.
62 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
63 (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
64 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
65 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
66 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
67 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
68 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
69 }
70 else
71 {
72 //Otherwise the write timing configuration register is invalid
73 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
74}
75}