Table of Contents
1. Background
2. Max/Min_delay constraints
2.1 Constraint setting parameters
2.2 Constraint description
3. Project examples
3.1 Engineering code
3.2 Timing report
4. Reference materials
1. Background
In the design, sometimes it is necessary to limit the maximum delay and minimum delay of the path, such as asynchronous signals without specific clock relationships, but the maximum delay and minimum delay need to be limited, and the path from port to port (no register in the middle) can also be limited. Set the maximum delay and minimum delay. Setting the maximum delay and minimum delay will affect the current setup and hold timing analysis.
2. Max/Min_delay constraint
The commands to set the maximum delay and minimum delay of the path are set_max_delay and set_min_delay. You can enter Exceptions in the Timing Constraints window and select Set Maximum Delay or Set Minimum Delay to select the maximum delay or minimum delay.
2.1 Constraint Setting Parameters
Take setting the maximum delay as an example. Double-click Set Maximum Delay to enter the setting window.
Targets settings
Specify path delay: Set the maximum path delay value, which can be a positive or negative integer.
From: Set the starting point of the path, the object can be Clocks, Cells, Cell pins, I/O ports
Through: Set the intermediate passing point of the path, the object can be Net, Cells, Cell pins
To: Set the end point of the path, the object can be Clocks, Cells, Cell pins, I/O ports
Options settings
Rise/Fall: When checked, the maximum delay can be set. It is only valid for rising edge trigger or falling edge trigger paths. When unchecked, edge triggering is not distinguished.
Set Maximum…ignored): The delay constraint set after checking is only valid for the data path. The clock skew and hold checks will be ignored, which is equivalent to the path also having set_false_path – hold constraint, if set_min_delay constraint is set in the constraint, it will not take effect. And this setting cannot be used in set_min_delay constraints.
Remove…path delays: When checked, if there are other exception constraints on the set constraint path (such as false_path, multicycle constraints, maximum and minimum delay constraints will be removed)
2.2 Constraint Description
For input and output logic constraints, set_max_delay/set_min_delay will not be used. For the logical path from the input port to the first-level register or the last-level register to the output port, set_input_delay is usually used.
/set_output_delay constraints,set_max_delay/set_min_delay are usually used to constrain purely combinatorial logic paths between input ports and output ports.
Another commonly used scenario for set_max_delay is asynchronous signals that have no clock relationship, but the maximum delay needs to be set. Two asynchronous clock paths can use set_clock_group or set_false_path so that timing analysis does not occur. When the design between asynchronous clocks is reasonable, such as the two-level synchronization register in the FIFO, to relax the constraints and ensure that the path delay between the two clocks meets the actual situation, set_max_delay needs to be used.
In a multi-bit cross-clock domain (CDC) scenario, the skew between bits must be within a certain required time. Although the skew can be constrained by set_bus_skew, it must be ensured that the delay between the two clock domains cannot be too large. At this time, you can replace set_false_path/set_clock_groups by constraining set_max_delay -datapath_only.
If the maximum delay for some or all paths between two clock domains must be clear, the set_max_delay -datapath_only constraint must be used. In this scenario, set_clock_groups cannot be used to define two clocks as asynchronous clocks, because it will replace set_max_delay from the perspective of constraint priority. Other cross-clock domain paths must be jointly constrained with set_false_path or set_max_delay constraints.
2.3 Path segmentation
Different from other constraints in the constraint file of. When an invalid start point is set, timing analysis tools prevent the timing path from passing through the node in order for the node to become a valid start point.
Taking the following constraints as an example, the starting point of the maximum delay constraint is the effective starting point
set_max_delay 5 -from [get_pins FD1/C]
If the constraint is set to FD1/Q, the timing analysis tool will break the path from C->Q, making pin Q a valid starting point. This practice of disconnecting the timing path in order to create an effective starting point is called path segmentation. Path segmentation will have an impact on the maximum delay and minimum delay, and will also affect the nodes passing through these nodes (FD1/Q, FD1/ C) timing constraints.
set_max_delay 5 -from [get_pins FD1/Q]
Impact of path segmentation
Orderly setting of maximum/minimum delays results in path segmentation, and there will be no startup clock for the timing path from the starting point FD1/Q because the clock skew at the end point will be taken into account. Therefore, it will be possible to cause large clock skew, as shown in the figure below.
After the path is segmented, there will be no default hold requirement time. If the -datapath_only option is not selected, use the set_min_delay command to set the hold requirement time. Officially, because segmentation brings risks, an alarm will appear when a path segmentation occurs.
If you must output FD1/Q as the most constrained starting point and do not want to consider the impact of clock skew, you can check -datapath_only to solve the problem.
set_max_delay 5 -from [get_pins FD1/C] -datapath_only
Similarly, if an invalid end point is set, path segmentation will also occur in order for the node to become a valid end point.
Taking LUTA/O as the end point as an example
set_max_delay 5 -from [get_pins LUTA/O]
In order to make LUTA/O a valid end point, the timing analysis tool will disconnect the path behind LUTA/O. Therefore, all setup/hold paths passing LUTA/O will be affected. For REGA/C as the starting point and LUTA/O For the path to the end, the clock skew will be large.
In the image below, set the constraints
set_max_delay 6 -from [get_pins LUTA/O] -to [get_pins REGB/D]
Since LUTA/O is not a valid starting point, path fragmentation will occur at LUTA/O and the timing path from LUTA/I0 to LUTA/O will be broken. Although the constraint is only set between LUTA/O and REGB/D, the path from REGA/C to REGC/D is also affected and disconnected.
Path segmentation and timing exceptions
Path segmentation may also cause priority alarms for timing exceptions, especially for set_clock_groups and set_max_delay, such as the following two scenarios
Scene 1
set_max_delay <ns> -datapath_only -from <instance> -to <instance>
The maximum delay constraint is set in two instances. If the instance has a set_clock_groups -asynchronous constraint, the set_max_delay constraint will be overridden when vivado selects a valid starting point of the instance.
Scenario 2
set_max_delay <ns> -datapath_only -from <pin> -to <pin | instance>
The constraint is from the pin to the inst pin. At this time, if the instance has a set_clock_groups -asynchronous constraint, the set_max_delay constraint will not be overridden. The reason is that path segmentation will make the path start pin no longer considered the start of the first clock domain, so set_max_delay will not be overridden and the constraint will be valid.
3. Project Example
3.1 Project Code
Taking the cross-clock domain path ff1_reg/C to ff2_reg/D as an example, the design code
module timing(d1,d2,clk1,clk2,ce,ff2);
input d1,d2,clk1,clk2,ce;
outputff2;
reg ff1,ff2;
wire comb;
always@(posedge clk1,negedge ce)
begin
if(!ce)
begin
ff1<=0;
end
else begin
ff1<=d1;
end
end
assign comb=ff1 &d2;
always@(posedge clk2,negedge ce)
begin
if(!ce)
ff2<=0;
else begin
ff2<=comb;
end
end
endmodule
Netlist connection
Constraint settings
set_max_delay -from [get_pins ff1_reg/C] -to [get_pins ff2_reg/D] 5.000 //Set the period of clk
set_min_delay -from [get_pins ff1_reg/C] -to [get_pins ff2_reg/D] 2.000 //Set the period of clk2
create_clock -period 10.000 -name clk1 -waveform {0.000 5.000} [get_ports clk1] //max_delay value is 5
create_clock -period 7.000 -name clk2 -waveform {0.000 3.500} [get_ports clk2] //min_delay value is 2
3.2 Timing Report
In the timingreport summary, check the inter-clock paths to view the cross-clock domain paths. In the setup analysis, the setup requirement is the set_max_delay value of 5ns.
The requirement value of hold analysis is set_min_delay value 2ns
On the destination clock path, the delay value is directly added to the set delay value.
Summary: The value set by set_max_delay is the setup Requirements value of the path, and the value set by set_min_delay is the holdup Requirements value of the path
4. Reference materials
User Manual: ug903-vivado-using-constraints-en-us-2022.2.pdf
Link: https://pan.baidu.com/s/17AK_-J4wRXiFLtLTorlrwg?pwd=mylt
Extraction code: mylt