This article describes the use of HDLBits for online comprehensive simulation of FPGA code and generation of timing diagrams to verify your own design.
After studying this tutorial, you can easily build your own simulation by checking the “Summary of necessary simulation elements” each time!
Article directory
- Introduction to HDLBits
- Online simulation rule learning
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- Official template
- :key: Summary of necessary elements for simulation
- Web interface usage operations
- Example demonstration to verify your own design
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- RTL writing
- Testbench writing
- Summarized into a .v file
- Simulation results
- Timing diagram export
- Compilation error modification
- Separate top_module simulation
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- Write top_module module
- Compilation information and timing diagram viewing
Introduction to HDLBits
HDLBits is best known as a web version of Verilog code editing simulation verification platform. This platform is a foreign open source FPGA learning website. Enter the web page through the address “https://hdlbits.01xz.net/wiki/Main_Page” , on this web page, you can write and synthesize Verilog code, and finally can simulate waveforms to verify the correctness of the design code. The verification platform is based on Icarus Verilog (referred to as iVerilog, a well-known open source HDL simulation tool, which also has a corresponding installation version), allowing you to enjoy the fun of Verilog programming simulation anytime and anywhere just by logging in to the web page!
It is a website that is very suitable for Verilog beginners to get started quickly. It includes exercises on Verilog syntax, combinational logic, sequential logic, simulation, etc. Your code in the web page will be synthesized into a hardware circuit through the Altera Quartus synthesizer. Your integrated circuit is checked for correct functionality through functional simulation. HDLBits uses ModelSim to simultaneously simulate your code and a reference solution, then compare the output of the two.
More comprehensively, it also contains tools to help you learn the basics of computer design, including HDLBits, ASMBits, and CPUlator. Enter the web page through the address ”https://www.01xz.net/wiki/Main_Page”.
HDLBits: Problem sets and online judgments for practicing digital circuit design in Verilog;
ASMBits: Just like HDLBits, but for practicing Nios II or ARMv7 assembly language;
CPUlator: In-browser full-system MIPS, Nios II and ARMv7 emulator and debugger.
Online simulation rule learning
In addition to being used for Verilog practice, HDLBits can also be used for online comprehensive simulation of FPGA code and timing diagram generation to verify your own design, allowing you to run any simulation you want.
Click “Run a Simulation (lcarus Verilog)” under Simulation in the upper left corner of the web page.
Official template
First, we use the official template to learn how to use the simulation function.
The official template code is as follows:
module top_module ();
reg clk=0;
always #5 clk = ~clk; // Create clock with period=10
initial `probe_start; // Start the timing diagram
`probe(clk); // Probe signal "clk"
// A testbench
reg in=0;
initial begin
#10 in <= 1;
#10 in <= 0;
#20 in <= 1;
#20 in <= 0;
$display ("Hello world! The current time is (\r ps)", $time);
#50 $finish; // Quit the simulation
end
invert inst1 ( .in(in) ); // Sub-modules work too.
endmodule
module invert(input in, output out);
assign out = ~in;
`probe(in); // Sub-modules can also have `probe()
`probe(out);
endmodule
Summary of necessary elements for simulation
Based on the official template, the elements required for simulation are summarized.
First of all, to simulate FPGA logic, you must have two files. One is the RTL code file, which is used to comprehensively generate the hardware circuit part; the second is the Testbench file, which is the simulation file used to verify the function of the RTL code. The two lack Not even one. Here you need to write both RTL code and Testbench in an edit box.
Secondly, “initial probe_start” on line 4, “probe(clk)” on line 6, and “probe(in)” on line 26 are an officially defined “macro”, that is, called through this “macro” For the function of “probe” probe, we don’t need to worry about how this “macro” is defined, we only need to be able to call it. Note that this is not a syntax in Verilog, it is only used for waveform drawing in web page simulation.
Therefore, the necessary elements when writing code in the code editing area are as follows:
| Elements | Code location |
|---|---|
| RTL code and Testbench are written in In an edit box, the order of the two is arbitrary | There are two modules in line 1 and line 23, and they end with endmodule respectively |
| You can also< strong>Use a separate top_module for simulation | The section “Single top_module simulation” at the end of this article is explained |
| The simulation file name must be “top_module” | Line 1 |
| initial `probe_start; | Line 4, for Start the timing diagram |
| `probe(XX); | Lines 6, 26, and 27, the signals in brackets indicate the signals that need to be drawn |
| #50 $finish; | In line 16, be sure to set the simulation stop time. If the simulation end time is too long, you will be prompted |
The following adds the usage and limitations of timing diagram drawing: each signal can only be added once. There can be up to 512 signals. Each signal can be a bus of no more than 512 bits.
Web interface usage operations
- Click ”Submit”. The compiled information and simulation waveforms will appear at the bottom of the current page.
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Click “Submit(new window)” to simulate in the new interface. The compiled information and simulation waveforms will appear in the newly opened interface.
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Click ”Share”, the page code will be generated into a web page, and you can share it with others.
- You can also put the written Testbench code and RTL code into the same local .v file, then click “Upload a source file…” under the code editing box below, and select to add the .v file in the expanded interface. Then click “Upload and simulate” to start the simulation.
Example demonstration to verify your design
Let’s take this example truth table as an example https://hdlbits.01xz.net/wiki/Truthtable1 for demonstration. Input signals x3, x2, x1; output signal f. Write Verilog code and simulate and draw timing diagrams.
| Row | Inputs | Outputs | ||
|---|---|---|---|---|
| number | x3 | x2 | x1 | f |
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 |
| 2 | 0 | 1 | 0 | 1 |
| 3 | 0 | 1 | 1 | 1 |
| 4 | 1 | 0 | 0 | 0 |
| 5 | 1 | 0 | 1 | 1 |
| 6 | 1 | 1 | 0 | 0 |
| 7 | 1 | 1 | 1 | 1 |
