Table of contents of FIFO series articles: Verilog function module – asynchronous FIFO-CSDN blog Verilog function module – synchronous FIFO-CSDN blog Verilog function module – asynchronous FIFO with different read and write bit widths-CSDN Blog Verilog function module – synchronous FIFO with different read and write bit widths-CSDN Blog Verilog function module – standard FIFO […]
Tag: fifo
Verilog function module – asynchronous FIFO
Table of contents of FIFO series articles: Verilog function module – asynchronous FIFO-CSDN blog Verilog function module – synchronous FIFO-CSDN blog Verilog function module – asynchronous FIFO with different read and write bit widths-CSDN Blog Verilog function module – synchronous FIFO with different read and write bit widths-CSDN Blog Verilog function module – standard FIFO […]
[Inter-process communication] Pipe communication {The purpose of inter-process communication; Common methods of inter-process communication; Anonymous pipe: Implementation principle, pipe symbol |, system call pipe, process pool; Named pipe: mkfifo instruction, system call mkfifo}
1. The purpose of inter-process communication Most of the code we wrote before was a single-process task. A single process cannot use the concurrency function of the process, nor can it realize the collaborative work of multiple processes. Therefore, we need to implement multi-process tasks, and the key to multi-process is inter-process communication. Inter-process communication […]
FPGA project: fifo_sum
Experiment goal: col(column) = 4; line(row) = 5. Three adjacent rows are summed by column. Output a new data stream. Implementation method: Through rs232 communication protocol, input data stream. The first line is stored in fifo1, and the second line is stored in fifo2. When the first data of the third line is input, the […]
FPGA project: FIFO_SUM
Expansion training: 5X5 matrix, sum three adjacent columns. Data is still transmitted in the form of a data stream (rs232), and data is transmitted out in the form of a data stream. Analysis: 1. In fact, this can be achieved using two fifos with a depth of 2. And the row counter is no longer […]
Microcontroller programming ideas and routines 5 – circular queue (fifo+serial port)
Table of Contents Preface Circular Queue Principle Function realization Routine (serial port sending and receiving) write at the end Foreword Speaking of queues, I believe everyone has used them more or less. Some commonly used operating systems are integrated inside and users can use them directly. But if we are asked to implement a queue […]
ZYNQ experiment FIFO reading and writing experiment (how to balance reading and writing across clock domains)
1. Experiment introduction Basic principles reference article: ZYNQ experiment-IQ modulation implements SSB PART1. This experiment will implement the data forwarding function between PS-PL in the reference article. In the experiment, the data on the PS side is stored in DDR, and the PS side converts the data into stream mode output through AXI-stream FIFO. The […]
Verilog function module – standard FIFO to FWFT FIFO
Preface When using the FIFO IP core, I prefer to use FWFT (First Word First Through) FIFO instead of standard FIFO. The data of FWFT FIFO will be preloaded to the dout port. When empty is low, the data is already valid, and the rd_en signal is Instructs this FIFO to update the next data. […]
Implementation of OPT, FIFO, and LRU algorithms
1. Experimental Purpose Understand the characteristics of virtual storage technology, master the basic ideas and implementation processes of several basic page replacement algorithms in virtual storage request page storage management, and compare their efficiencies. Understand programming techniques and the causes of memory leaks Second, Experimental Content Simulate several basic page replacement algorithms for request page […]
Simulation and synthesis technology of asynchronous FIFO design (6)
Overview The main body of this article is translated from the article C. E. Cummings and S. Design, “Simulation and Synthesis Techniques for Asynchronous FIFO Design”, with the author’s personal understanding and comments added. The blue part of the article is the author’s notes or free translation. Previous link: Simulation and synthesis technology of asynchronous […]